Outline Test points and Scan Built-In Self-Test (BIST) Introduction to structured Systems-on-chip test VLSI design Boundary scan (IEEE 1149.1) Design for Test (DfT) - Part 2 Erik Larsson EIT, Lund University Integrated Circuits (IC) AND-gate Die Viper 2.0 RevB Analog/Digital TV Processor 10mm x 10 mm (100 mm 2 ) ~10 M gates ~50 M transistors ~100 clock domains
IC Manufacturing IC Manufacturing Chemical or plasma etch Si-substrate Hardened resist The cost to set up a modern SiO 2 45 nm process is $200–500 (a) Silicon base material Si-substrate million Photoresist SiO 2 The purchase price of a (d) After development and etching of resist, chemical or plasma etch of SiO 2 Si-substrate photomask can range from $1,000 to $100,000 for a Hardened resist (b) After oxidation and deposition SiO2 of negative photoresist single mask. Si-substrate UV-light As many as 30 masks (of Patterned (e) After etching varying price) may be optical mask required to form a complete Exposed resist SiO2 mask set. Si-substrate Si-substrate (f) Final result after removal of resist (c) Stepper exposure IC Defects Fault Models A defect manifests itself as a fault A fault is modeled by a fault model Example of fault models: Stuck-at Fault, Bridging Fault, Shorts (Resistive shorts), Opens, Delay Faults, Transient Fault Seed So far stuck-at fault model is the most used one: Salt Motivations: Simple and covers quite well possible defects
Stuck-at Fault (SAF) Model Deterministic Test Generation While fault coverage < desired limit { Select an uncovered fault f A line is fixed to logic value 0 (stuck-at-0) or 1 (stuck-at-1) Generate test for the fault f For the stuck-at fault model there are for a circuit with n lines Evaluate fault coverage 2*n possible faults } G3 G5 Needed functions to generate a test: U G2 G NOR Z G1 W OR Excite (provoke) the fault A AND NOR B F Sensitize (propagate) the results to primary outputs X G4 H Justify other values in the circuit AND Y ATPG: D-algorithm Path-Oriented Decision-Making (PODEM) Quality of a test is given by: fault coverage = faults detected / total number of faults Fanout-oriented Test Generation (FAN) Structure-oriented cost-reducing automatic test pattern generation (SOCRATES) Example: 12 lines (24 faults) detect 15 faults: f.c.=15/24 (63%) Commercial ATPG Tools Test Point Insertion Commercial ATPG tools are often for combinational circuits 0-control point Commercial tools usually make use of a random test generation for 60-80% of the faults (easy to detect) and deterministic test generation for the remaining part (hard to detect) 0 Stuck-at 1 G3 G1 Examples of commercial ATPG tools: G5 X F A AND NOT H L Encounter Test - Cadence X AND X G2 TetraMax - Synopsis B G X OR C K FastScan, FlexTest - Mentor Graphics X G4 E NOT
Test Point Insertion Sequential -> Combinational OP Problem: ATPG works for combinational logic while most ICs are sequential Solution: Provide a test mode in which flip flops can be accessed directly Observation Original Register provide virtual primary inputs/primary outputs PO Write flip flops PI PI PO 1. Combinational Combinational Combinational Combinational 0 M Stimulus at inputs logic logic 2. logic logic U Normal cycle 3. 1 X Flip flops Flip flops launch/capture CP Observe output CP 4. CP1 Read flip flops 5. CP2 0-controllability 1-controllability 1/0-controllability Scan Design Concept Sequential -> Combinational Circuit can be in two modes: Functional mode and Test mode SFF SE In Test mode test data can be shifted in and shifted out FF D FF D Q MUX SI Q Test mode adds virtual PI and PO such that test data can be CLK CLK directly applied to combinational logic SO ATPG for combinational logic works also for sequential SE: Scan enable SI: Scan input SO: Scan output PI PI PO PO Combinational Combinational Combinational Combinational Write flip flops 1. logic logic logic logic Stimulus at inputs 2. Replace flip flop (FF) with scan flip flop (SFF): extra multiplexer Normal cycle 3. Flip flops Flip flops on data input launch/capture Observe output 4. Connect SFFs to form one or more scan chains Read flip flops 5. Connect multiplexer control signal to scan enable
Scan Test Application - first attempt Scan Test Application - second attempt Scan chain 1 (6 FFs) Scan chain 1 (6 FFs) SO SO SI SI Test time=number of patterns Test time=number of patterns *(shift-in + capture + shift-out)= *(shift-in + capture) + shift-out= 3*(6+1+6)=39 3*(6+1)+6=27 Combinational Combinational logic logic Z[0:2] Z[0:2] A[0:4] A[0:4] SE SE Capture Capture Capture Capture Capture Capture Shift-in Shift-out Shift-out Shift-in Shift-out Shift-in Shift-in/out Shift-in/out Shift-out Shift-in SE: 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 SE: 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 SI: SI: A[0:4] A[0:4] stimulus response stimulus response stimulus response stimulus resp/stim res/stim response Scan Benefits and Costs Delay Test Scan Benefits Stuck-at-fault test consist of one vector. Each vector applied at Scan Costs slow speed (DC-scan). Automatic scan insertion Silicon area - Mux, scan ATPG Timing related faults need two vectors and they are to be applied chain, scan enable on consecutive clock cycles (at normal clock speed) (AC-scan) High fault coverage Performance reduction - Multiplexer in time-critical path At speed test: Short test development time IC pins - Scan-in (SI), scan- Vector V1 is applied to set the circuit in its state out (SO), scan_enable (SE) Vector V2 is applied EDA tools Test time - Serial shifting is Response is captured For scan insertion (converting slow flip flops to scan flip flops) Three approaches: Connection Launch-on-capture Partial scan selection Launch-on-shift Scan stiching Enhanced scan
Launch on shift (LOS) and launch on LOS and LOC capture (LOC) DC scan SE Launch on capture (broadside or double capture) shift in test stimuli (usually at low speed). For an n-bit shift register, CLK shift in n bits. apply a capture to create transition LOC SE apply another capture cycle to capture the response Launch on shift (skewed load) CLK shift in test stimuli (usually at low speed). For an n-bit shift register, shift in n-1 bits at low speed. LOS The final bit is shifted at high speed and then a capture is applied in SE high speed. CLK Enhanced Scan Outline SFF SFF SE SE Test points and Scan FF D D Q MUX Built-In Self-Test (BIST) Q SI SI CLK CLK SO Systems-on-chip test Boundary scan (IEEE 1149.1) SE: Scan enable SI: Scan input SO: Scan output UPDATE C LA SFF SE Q D D SO Q SI CLK
Built-In Self-Test On-chip/off-chip ATE Key component to discuss: Device under test (DUT) Test source Test pattern storage/generation Off-chip Test stimuli storage/generation Test sink Test response analysis Test control In a non-BIST environment: Test source Device under test (DUT) test generation is performed by ATPG; a tool such as FastScan can generate deterministic test patterns, On-chip test stimuli and expected test responses are stored in the ATE, and Test sink the ATE controls the testing and performs test evaluation. Test Pattern Generation Test Pattern Generation How store/generate test patterns on-chip? Exhaustive test generation; simple hardware (a counter), 100% fault coverage but too time consuming Deterministic test generation; high fault coverage but requires Deterministic test patterns ATE for test pattern storage Exhaustive test patterns Pseudo-exhaustive test generation using Linear-Feedback Pseudo-exhaustive/random test patterns Shift-Registers (LFSR) Random test patterns + Commercial tools usually make use of a random test generation for 60-80% of the faults (easy to detect) and deterministic test FF FF FF FF generation for the remaining part (hard to detect)
Test generations Random Pattern Resistant Faults The effectiveness of a test is given based on the test’s fault Some logic takes too long to test with pseudo-random patterns coverage, length, and hardware/data storage requirement. Too many specific input bit values are required Probability to create a 1 at the output; 1/2 n where n is the Too many pseudo-random trials needed to achieve the required number of inputs. n=2; P=0.25, n=4; P=0.0625 value combination AND AND Test Response Analysis Response Compaction: Motivation How store/analyze test responses on-chip? Compaction of test responses necessary for verifying the test response Compression – does not loose information Store compacted response called signature and Compaction – does loose information compare to known fault-free signature Compaction alternatives: Fault-free Parity check signature One counting (W bits) N >> W Transition counting Signature analysis Response = Test Pass/fail compaction response circuit (N bits)
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