Integrated Systems Integrated Systems Challenges and Opportunities - PowerPoint PPT Presentation

Integrated Systems Integrated Systems Challenges and Opportunities Challenges and Opportunities Giovanni De Micheli Giovanni De Micheli Centre Syst Systè èmes mes Int Inté égr gré és s Centre

Integrated systems • Ubiquitous presence of integrated circuits and systems in products • The market pull: – Run demanding SW applications with minimal energy consumption • The technology push : – Pushing the physical limits of computational structures 2 De Micheli

Anecdotes • I think there is a world market for maybe 5 computers - T. Watson – IBM, 1949 • There is no reason anyone would want a computer in their home - K. Olsen – DEC 1977 • I see no advantage whatsoever to a graphical user interface – B. Gates - Microsoft, 1983 • The cost of silicon in a car is higher than the cost of steel - circa 2000 • Communications of ACM dedicates a full issue to internet games - November 2006 3 De Micheli

Multi-processor Systems on Chips • Large-scale systems – Billion-transistor chips – Multi-cores, multi-threaded SW – Power-consumption limited • Very expensive to design IBM Cell Multi-Processor – Non recurring engineering costs – Require large market 4 De Micheli

Platforms • Address application-specific needs – Domain-specific hardware – Differentiation via software • Examples – Telecom: • Philips Nexperia • ST Nomadic – Automotive 5 De Micheli

Designing a large chip USB PHY USB PHY Ethernet PHY Ethernet PHY Custom Custom SDRAM SDRAM CPU CPU USB 2.0 USB 2.0 Block Block Ethernet Ethernet I/F I/F ISB 1.1 ISB 1.1 Arbitration Arbitration & Decode & Decode AMBA AHB AMBA AHB & Mux & Mux Boot Boot AHB/APB AHB/APB AHB/ AHB/PCIe PCIe SATA SATA Interrupt Interrupt 1394a 1394a Bridge Bridge Bridge Bridge Rom Rom Controller Controller 1394 PHY 1394 PHY SATA PHY SATA PHY AMBA APB AMBA APB PCI Express PCI Express Watchdog Watchdog GPIO GPIO UART UART Timer Timer PCIe PHY PCIe PHY 10 3 Blocks System Process begin Wait until not Clock = 1; If (Enable =‘1’) then 10 5 Toggle = Not Toggle; RTL lines RTL Endif End process; 10 8 Gates Netlist 10 9 Transistors Circuit 10 12 Polygons Layout 10 13 Trapezoids Mask CMOS, mostly digital, 65nm, >200mm 2 6 De Micheli

Challenges & solutions • Complexity (giga scale) • Synthesis technology – Model HW with languages – Intractable large scale problems – Compile into masks • Technology (nano scale) – Ever shrinking CMOS – New disruptive technologies • Issues • Architectures – Design closure – Multi-processing – Handling new technologies – Structured communication – HW/SW co-design • Objectives – Deal with multiple objectives – High performance – Verifying correctness – Low-energy consumption – … – Small footprint - low cost – Dependable 7 De Micheli

Outline • The nanotechnology challenge – Variability management – Error tolerance • The energy consumption challenge – Temperature management • The communication bottleneck – Networks on chips • A vision and conclusions 8 De Micheli

Where are we heading? • Medium term: – More Moore • More scaling - More complex chips - Fewer players – More than Moore • Use silicon technologies beyond computational structures • Interaction with environment, sensors, etc… • System integration Sensor Sensor • Long term: – A multi-furcation of Moore’s scaling law beyond the 22 nanometer node – New technologies: • There is plenty of room at the bottom 9 De Micheli

Will a new nano-electronic technology prevail? • The skeptical view: – Investments in CMOS silicon are huge – We will not need localized computing power beyond what is achievable with a 1 cm 2 die in 22 nm silicon CMOS – Wiring is the bottleneck: making transistor smaller does not help • The optimistic view: – We will always need increasing computing power and storage capacity – We need to curb the increasing costs of manufacturing – We will invent new computing architectures, storage media and communication means 10 De Micheli

How is the transition path? • When will current semiconductor technologies run out of steam? • What factor will provide a radical change in technology? – Performance, power density, cost? • Will the transition eliminate previous CMOS technologies? – Are the new nanoelectronic technologies compatible with standard silicon? • How will we design nanoelectronic circuits: – What are the common characteristics, from a design technology standpoint? 11 De Micheli

Common characteristics of nano-devices • Self-assembly can be used to create structures – Manufacturing paradigm is both bottom-up and top down – Attempt to avoid lithography bottleneck • Combined presence of micro and nano-structures – Interfacing and compatibility issues • More physical defects and higher failure rates – 10-15% defective devices according to recent estimates – Design must deal with nonworking and short-lived devices • Advantage stems from the high density of devices – Two orders higher than scaled CMOS 12 De Micheli

Design issues • Variability – Physical parameter variation – Molecular structural effects • Reliability – Higher failure rate – Higher environmental exposure – Transient and permanent errors 13 De Micheli

Variability • Variations within/across chips – Fast/slow transistors and interconnect • Design objective: – Achieve better than worse-case performance • Solutions – Statistical timing analysis – Statistical logic synthesis – Asynchronous design – System-level approaches 14 De Micheli

Self-calibrating circuits n FIFO Controller • Adapt to inter-chip variations and to environmental changes errors F ch v v – Use on-line adaptation policy v v dd dd Encoder ch ch Decoder • Examples: FIFO – Dynamic voltage scaling of bus swings [Worm,Ienne –EPFL] Ack – Dynamic voltage scaling in processors • Razor [Austin – U Michigan] clk – Dynamic latency adjustment for NoCs • Terror [Tamhankar -Stanford] D1 Q1 0 Main • Autonomic computing 1 Flip-Flop Error_L – Systems that understand and react to Shadow environment [IBM] Latch comparator Error RAZOR FF clk_del 15 De Micheli

Reliability: coping with transient malfunctions • Soft errors – Data corruption due external radiation exposure • Crosstalk – Data corruption due to internal field exposure • Both malfunctions manifest themselves as timing errors – Error containment 16 De Micheli

Soft error rates • Vary with altitude and latitude 17 De Micheli

Propagation of soft errors 18 De Micheli

Logic protection techniques Redundancy (TMR) Detection + System Hardened Other Correction Libraries Techniques MODULE D Q DFF D Q Data Out Combinational D Q clock Logic VOTE Comp ERR DUPLICATED Clock Sequential MODULE Element scan in scan out D Q δ scan clock TRIPLICATED clock DFF Dup MODULE Scan Sequential Protection Element Transistor embedded in 100% to 200% overhead ERR signal used by system SCAN hardware used as the cell (Hardware or Software) to DETECTION hardware in correct the error functional mode Redundancy Shielding Others [Source IROC] 19 De Micheli

Failure rate Reliability: aging of materials time • Failure mechanisms: – Electromigration – Oxide Breakdown – Thermo-mechanical stress • Temperature dependence – Arrhenius law – Gradients 20 De Micheli

Summary: coping with variability & reliability • Design chips so that they are insensitive to local timing variations • Exploit redundancy to replace failing devices • Manage power consumption and temperature of on-chip components 21 De Micheli

Outline • The nanotechnology challenge – Variability management – Error tolerance • The energy challenge – Temperature management • The communication bottleneck – Networks on chips • A vision and conclusions 22 De Micheli

Thermal map 1.5 GHz Itanium-2 Cache Temp ( o C) Execution core AGU 120 o C [Source: Intel Corporation and Prof. V. Oklobdzija] 23 De Micheli

Thermal map: multiprocessosr 24 De Micheli

Thermal management modeling Thermal Sleep Policy Manager E nvironment Queue System Active Active 4 3 2 1 Idle Idle Sleep 25 De Micheli