Innovation to Advance Moores Law Requires Core Technology Revolution - PowerPoint PPT Presentation

Innovation to Advance Moore’s Law Requires Core Technology Revolution Klaus Schuegraf, Ph.D. Chief Technology Officer Silicon Systems Group Applied Materials UC Berkeley Seminar March 9 th , 2012 External Use

Innovation to Advance Moore’s Law Thank you for coming Semiconductor Value Chain - Equipment Moore’s Law Challenges Opportunities for Innovation Core Technology Focus External Use 2

APPLIED WAFER INTEGRATED DEVICES MATERIALS FAB CIRCUITS DRAM VERTICAL TRANSISTOR LOGIC FINFET NAND VERTICAL BIT STACK 3 External Use

Leadership Strategy - Accelerate Innovation Collaborate earlier and deeper with customers on inflections Deposition Thermal Provide the broadest suite of solutions with unmatched integration benefits Extend the technology roadmap Metals Planarization with fast cadence in product innovation Drive to atomic precision on interfaces with multi-chamber platforms Inspection Etch Enable faster learning with Maydan Technology Center Plating Implant 4 External Use

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Moore’s Law in Context Cost Performance Moore’s Law: Performance, Power Efficiency, Cost From: W. Nordhaus, Yale 6 External Use

Logic Technology Scaling Projection Logic Roadmap Scenario 2009 2011 2013 2015 2017 2019 2021 2023 2025 2027 Node and Lg (nm) 32 22 14 10 7 5 3.5 2.5 1.8 1.3 Interconnect CD (nm) 60 40 30 20 15 10 7.5 5 3.5 2.5 Planar CMOS FinFET III-V FinFET Gate New Fin Material Fin STI STI Oxide Oxide Identify challenges and opportunities to enable scaling Focus university research on the big problems External Use 7

Inflections Add Complexity and Opportunity Advanced Advanced Advanced Wafer-Level Transistors Interconnects Patterning Packaging 8 8 External Use

Increasing +  Scaling Innovation Complexity Add to Big 3: Image sensor, MRAM, RRAM TODAY Big 3: Logic, DRAM, NAND Global innovation US-centric innovation Extreme customer concentration Fabless  Vertical fabless system houses Customer consolidation, JV partnerships Logic  Foundry/Fabless 300mm  450mm Logic  FinFET NOR  NAND DRAM 8F 2  6F 2 NAND  3D NAND DRAM 6F 2  3D 4F 2 200mm  300mm Single-wafer processing New energy sources: (E-beam, Laser, UV, X-ray) LAST NEXT 15 5 YEARS YEARS PVD  Metal CVD EUV E-beam inspection Double patterning for logic Deep-UV laser lithography Sacrificial films Quad patterning for memory Epi Memory Double patterning Single-wafer cleans CVD: Hidden films, more steps Laser-based processing Patterning films Copper damascene CMP: New materials, steps, Flowable films Lamp-based processing atomic precision New materials: III-V, Ge Low-k dielectric Reflow  HDP CMP Etch: New mtls, high aspect ratio Universal ALD (metal, dielectric) DRAM Capacitor Hi-K ALD Wafer-level packaging Bumping DPN SiON gate Packaging  interposer Optical interconnect 9 External Use

Advanced Transistor Challenges Gate Stack Dummy gate considerations Spacer Ternary materials Conventional approach: high AR gate Planarization Alternative: Spacer transfer Removal Alternative: Selective deposition Hi-k scalability Challenge: Spacer-k and Hi-k parasitic Metal gate considerations Workfunction Resisitivity Fill Self-aligned contact Fin Fin Junctions Conformal doping Stressor alternatives STI Annealing considerations Oxide Silicide Fin Formation Barrier modification Precision etch New materials Structural integrity (collapse, erosion, thermal shock) Recess Channel materials 10 External Use

Gate Dielectric Scaling Challenge 10 1000 Poly/SiON High-k/Metal 100 Gate Leakage (Rel.) 10 T INV (nm) 1 1 Slowed 0.1 2 nm Applied Internal Data Scaling EOT limited by 0.01 SiO2 IL 350 250 180 130 90 65 45 32 22 15 11 7 Technology Node (nm) Thinner EOT requires innovation in interfaces 11 External Use

Interfaces Matter Even More Electrically… Improved Mobility Less Trap Assisted Tunneling 5 to 10% - 30% Gate Leakage Peak Temperature Mobility Acceleration Applied Internal Data Applied Internal Data Air Exposure Fully Air Exposure Fully After Interface Integrated After Interface Integrated Layer Gate Stack Layer Gate Stack RadiancePlus RadiancePlus DPN3 ALD Centura cluster enables solution path Nitridation High-  12 External Use

New iL technology improves BTI Reliability NBTI PBTI ChemOx IL ChemOx IL 3A new IL delta Vt @ 1000 sec 0.1 0.1 3A new IL 5A new IL @ 5A new IL Applied Internal Data Applied Internal Data 0.01 0.01 0.6 0.7 Vg - Vt (V) Vg - Vt (V) 13 External Use

Advanced Interconnect Challenges( ≤ 20nm) Patterning Pitch division Reliability CD distributions, CDU Electromigration Overlay BLOk-Cu interface Pattern integrity Barrier-Cu interface Line bending, collapse TDDB/BTS LWR/LER Patterning(Overlay, LWR/LER) Interface management Barrier and moisture integrity Resistance Capacitance Copper Packaging Conformal barriers High modulus at lower k Liner/barrier Volume Interface adhesion Gap-fill Integrated k Scattering BLOk thickness Barrier-Cu interface Integration damage Grain size Higher k adhesion layers Higher aspect ratio Architecture Patterning Air-gap Gap-fill Single Damascene Non-Damascene External Use

Interconnect Improvement: RC-Delay RC Delay Outlook Disruptive 80 70 Conventional 60 RC Delay (ns/mm) Disruptive 50 40 30 20 10 Metal-Insulator Barrier 0 Replacement Low-k Diel. 32nm 22nm 15nm 11nm Low-k Dielectric Technology Node Copper Innovate new technologies to resolve RC-delay challenge 15 External Use

New Process Flow for RC Reduction 3 Applied Internal Data RC Product 0.99 SiN 2 0.95 0.90 BLOk % Probability 1 No damage 0.75 Cu-Low k interconnect 0.50 0 USG/Cu Interconnect Low k 0.25 -1 0.10 0.05 -2 Applied Internal Data Cu-Lowk BLOk Conventional flow -3 15% Damage Integrated k = Bulk k = No Damage No damage interconnect flow enables pathway to k < 2 16 External Use

Selective CVD Metal Caps for EM Enhancement 3 300°C, 1.5 MA/cm 2 0.99 2 0.95 0.90 % Probability 1 0.75 0.50 80x 0 0.25 -1 0.10 0.05 -2 -3 1 10 100 1000 10000 MTTF (hrs) Applied Internal Data Selective Metal Cap shows >80x EM improvement 17 External Use

Innovation to Advance Moore’s Law Semiconductor Value Chain - Equipment Moore’s Law Challenges Opportunities for Innovation Core Technology Focus External Use 18

Future of Moore’s Law S. Salahuddin, UCB, IEDM 2011 G. Dewey, Intel, IEDM 2011 T.-J. King Liu, UCB, IEDM 2009 Alternative Devices S. Bangsaruntip, IBM, IEDM 2009 Extend Gate all-around F. Yang, TSMC, VLSI 2004 FinFET 2D  3D Problem: Physical limits as features approach 3nm Need: Solutions to advance density, power and performance 19 External Use

New Device Scorecard  Packing density: Unit area per transistor (SRAM equiv.)  Performance: Switching delay  Power: Switching energy  Integration Complexity: Compatibility with Si CMOS Device Integration V op * SS Delay † Energy † Unit Area Compatibility (V) (mV/dec) (psec) (fJ) (nm 2 ) CMOS 32 nm High 0.9 <100 0.2 0.1 28000 CMOS 11 nm High 0.63 <70 0.02 0.03 3500 (extrapolated) CMOS 5 nm High 0.55 <70 0.01 0.015 900 (extrapolated) ? ? ? ? ? ? New Device *V op based on 2011 ITRS Roadmap for LOP † Inverter FO = 1, logic depth = 10, activity = 0.1 (Philip Wong, Stanford, IEDM 2010) External Use

Future of Moore’s Law: 3D GAA as alternative? “V dd ” Junction Conformal doping Gate Stack Conformal high-k and metal gate “Out” “In” Channel Patterning New channel materials Gates and junctions defined at planar level Local contacts and interconnect “Gnd” between planes Opportunity for new CMOS architectures with many challenges External Use

Focus Areas for Research  Core Technology – Energy sources – Chemical delivery systems & chemistries – E-beam – Variability management  Materials – Screening methods – Alternative materials: Graphene, Metal Oxide, III-V, optical  Devices – 100mV switches – High packing density logic – Alternate channel, Optical interconnect, Interposer  EUV Lithography 22 External Use