IIT Bombay CDEEP Autumn 2009 Introduction to IMAGE Simulation flow Presented by- Anil Powai Labs Tech. Pvt. Ltd. EE705/707 Lecture No. 25 Prof. M.Shojaei Baghini
IIT Bombay Hardware accelerated design simulation process • The designs are rapidly evolving, doubling in size with each generation and heading to tens million gates. • This causes dramatic increase of the simulation run time. The simulation time has increased from minutes and hours to days and weeks. • Therefore it is difficult to verify ASICs and system-on- chip (SoC) designs through software-only simulation. • Simulation assisted by special hardware is the best solution for speeding up the simulation of large design sections that have been tested and accepted by RTL simulations. EE705/707 Lecture No. 25 Prof. M.Shojaei Baghini
IIT Bombay Why hardware simulation is faster? • Assume a case where in the original RTL simulation the testbench is responsible for 10% of the simulation time . So for each 100 seconds of simulation time, 10 seconds are spent on executing testbench and 90 seconds on the design itself. • If we map the design portion from the software simulator into hardware, we could observe performance improvement in 90% of the simulation time because of concurrent behavior of hardware. EE705/707 Lecture No. 25 Prof. M.Shojaei Baghini
IIT Bombay Hardware accelerated design simulation process Software simulation Techbench/design Testbench Testbench/design top top Module C Module B Module C Hardware simulation Module A Module A & B Module A & B & C EE705/707 Lecture No. 25 Prof. M.Shojaei Baghini
IIT Bombay Hardware accelerated design simulation process Typically hardware accelerated design simulation process is carried out using a FPGA board. HDL Simulator FPGA Prototyping Board EE705/707 Lecture No. 25 Prof. M.Shojaei Baghini
IIT Bombay IMAGE : First look IMAGE is an integrated system of proprietary software tools, customized FPGA based hardware and distributed synthesis servers. The IMAGE system takes a specified design description and maps it to hardware system consisting of multiple FPGA’s and memory EE705/707 Lecture No. 25 Prof. M.Shojaei Baghini
IIT Bombay Mapping Design to IMAGE Hardware PCI DUT mapped to IMAGE HW IMAGE HW FPGA FPGA MEMORY MEMORY FPGA FPGA EE705/707 Lecture No. 25 Prof. M.Shojaei Baghini
IIT Bombay What is IMAGE ? Thus, IMAGE creates a map of user defined RTL onto pre-designed reconfigurable hardware. IMAGE can be used to select a section of simulation RTL, map it to FPGA hardware, and run the simulation in co-simulation mode with part of the simulation running on a host and part of it running on IMAGE FPGA hardware. EE705/707 Lecture No. 25 Prof. M.Shojaei Baghini
IIT Bombay Co-Simulation with IMAGE Simulator Simulator Test-Bench Test-Bench Design Top Design Top Instance1 Instance 1 Instance 2 IMAGE Hardware (DUT) Instance2 (DUT) Software Simulation IMAGE Co-Simulation EE705/707 Lecture No. 25 Prof. M.Shojaei Baghini
IIT Bombay Components in the IMAGE system • IMAGE mapping flow : A set of mapping tools that accepts an RTL description, analyses it, partitions it, and maps it a set of hardware boards. – This process is incremental in nature. i.e. if you make a small change in the RTL source, the turn-around time of the entire flow is correspondingly small. • IMAGE hardware : A set of hardware boards, each of which contains several FPGA's and a large amount of memory. – The mapping tool flow will partition the RTL across the available boards. • IMAGE synthesis flow : A set of management tools to coordinate the synthesis and compute servers needed to complete the mapping process. EE705/707 Lecture No. 25 Prof. M.Shojaei Baghini
IIT Bombay Components .. IMAGE server Work Node (IMAGE FLOW) LAN LAN IMAGE Mapping Synthesis Servers PCI Flow IMAGE Hardware IMAGE Synthesis LAN Flow The current capacity of an IMAGE system (using up to 12 cards) is 24 million ASIC gates with 200MB of memory. EE705/707 Lecture No. 25 Prof. M.Shojaei Baghini
IIT Bombay Features of the IMAGE system Mixed language: Support of VHDL/Verilog mixed design description with various signal coding schemes. Full type visibility from Hardware. Visibility of '0', '1', 'X','Z' in hardware. Multi-Clock: The IMAGE system allows the source RTL to have an arbitrary number of clocks, clock-gating logic and asynchronous descriptions. EE705/707 Lecture No. 25 Prof. M.Shojaei Baghini
IIT Bombay Features .. Controllability (ForceIT) and Observability (HookIN) Features: IMAGE permits the user to specify internal control and observation points which are then accessible from the host application. A SIG B C D Clk Rst EE705/707 Lecture No. 25 Prof. M.Shojaei Baghini
IIT Bombay Features .. Memory-Mapping (Mirage): IMAGE provides memory entities/modules which when used in the user RTL, enable the IMAGE tools to map these instances to on-board memory resources. The memory-mapping feature in IMAGE can model arbitrarily ported memories as well as ROMs. This can save FPGA resources, and increase the effective capacity of the hardware. EE705/707 Lecture No. 25 Prof. M.Shojaei Baghini
IIT Bombay Features .. Black-boxes, Un-synthesizable Entities: A black-box in IMAGE is a piece of already synthesized RTL which needs to be ”dropped-in” to the hardware. An un-synthesizable entity/module is a design unit which is marked by the user as a unit which cannot be synthesized; IMAGE will pull this unit out of the hardware and place it on the host-side for the co-simulation process. EE705/707 Lecture No. 25 Prof. M.Shojaei Baghini
IIT Bombay Features .. API and Simulator Interfaces: IMAGE comes with a full-featured API using which a user application that works together with the hardware can be constructed. IMAGE uses the Verilog-PLI/DPI interface link to a Verilog or mixed language simulator and the VHPI interface link to a VHDL only simulator. The DPI interface offers the highest performance. EE705/707 Lecture No. 25 Prof. M.Shojaei Baghini
IIT Bombay Incremental flow and Design Re-use The IMAGE mapping flow is incremental in nature. Small changes in the original RTL source do not need the entire process to be rerun: only the required part is run. This can lead to a turnaround time of a few minutes. In particular, a design unit that is already mapped to IMAGE hardware may be re-used in another simulation without having to repeat the mapping process. EE705/707 Lecture No. 25 Prof. M.Shojaei Baghini
IIT Bombay Features .. Distributed Synthesis server Setup: In the IMAGE system, one can configure a set of computers to act as servers in the IMAGE flow. These compute servers can be used to speed up the mapping process by parallelization. IMAGE allows monitoring and control of synthesis server. EE705/707 Lecture No. 25 Prof. M.Shojaei Baghini
IIT Bombay Feature : Distributed Server Setup EE705/707 Lecture No. 25 Prof. M.Shojaei Baghini
IIT Bombay Features .. IMAGE Flow Debugging: In order to track down the source of a possible mismatch between your software simulation and IMAGE accelerated simulation, the IMAGE installation includes a set of utilities which can allow you to break the IMAGE mapping flow at different points and to simulate the transformed RTL. EE705/707 Lecture No. 25 Prof. M.Shojaei Baghini
IIT Bombay Examples : IMAGE Flow Simulation of a design using IMAGE Flow is seamless. IMAGE can use an existing simulation setup based on standard simulators (e.g. Modelsim, VCS, GHDL, IcarusVerilog). EE705/707 Lecture No. 25 Prof. M.Shojaei Baghini
IIT Bombay Example1 : Mux .. Consider a example to illustrate the IMAGE Flow. We will denote the top entity/module from which analysis is to begin as the mux_tb, and the instance which is to be mapped to IMAGE hardware as the DUT. The DUT is a mux instance in VHDL, and we want to simulate the mux description using the mux_tb entity. EE705/707 Lecture No. 25 Prof. M.Shojaei Baghini
IIT Bombay Example1 : Mux .. The instance hierarchy of the design is as given below: top:mux_tb -DUT:u1 EE705/707 Lecture No. 25 Prof. M.Shojaei Baghini
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