IIT Bombay CDEEP Autumn 2009 Logic Simulation- Part II Elements of VHDL Presented by- Anil Powai Labs Tech. Pvt. Ltd. EE705/707 Lecture No. 19 Prof. Maryam Shojaei Baghini
IIT Bombay A Brief History Of VHDL • VHDL stands for Very high speed integrated circuit Hardware Description Language • Funded by the US Department of Defence in the 70's and 80's • Originally meant for design standardisation, documentation, simulation and ease of maintenance. • Established as IEEE standard IEEE 1076 in 1987. An updated standard, IEEE 1164 was adopted in 1993. In 1996 IEEE 1076.3 became a VHDL synthesis standard. • Today VHDL is widely used across the industry for design description, simulation and synthesis. EE705/707 Lecture No. 19 Prof. Maryam Shojaei Baghini
IIT Bombay Basic of VHDL • Entity – A design’s interface signals to the external circuitry. • Architecture – Describes a design’s behavior and functionality. • Configuration – Binds an entity to an architecture when there are multiple architectures for a single entity. • Package – Contains frequently used declarations, constants, functions, procedures, user data types and components. • Library – Consists of all the compiled design units like entities, architectures, packages and configurations EE705/707 Lecture No. 19 Prof. Maryam Shojaei Baghini
IIT Bombay Syntax entity entity_name is [generic generic_name : data_type [:= initial value ]] XOR gate [port port_name : port_direction data_type ] [ declarations ] [begin statements ] end entity_name ; -- comment library IEEE; Entity name –> xor_gate use IEEE.std_logic_1164.all; entity xor_gate is Generic : for passing parameter generic (p_delay : time:= 2 ns); port (ip1 : in std_logic; Port type –> std_logic ip2 : in std_logic; op1 : out std_logic ); Mode of the port :Direction of flow. end xor_gate; Port name –> ip1, ip2, op1 entity - defines the Interface. EE705/707 Lecture No. 19 Prof. Maryam Shojaei Baghini
IIT Bombay XOR gate Before accessing any unit in a library it needs to be declared . STD and WORK need not be declared . library IEEE; Library syntax is :- use IEEE.std_logic_1164.all; library library_name ; use library_name.package_name.item_name ; entity xor_gate is components declared inside a library can be generic (p_delay : time:= 2 ns); accessed by the ‘USE’ statement port (ip1 : in std_logic; Type ‘time’ is defined in package ip2 : in std_logic; STANDARD in library STD which op1 : out std_logic need not to be declare ); end xor_gate; Std_logic is the type of the port. It is defined in the std_logic_1164 package (present in IEEE library) std_logic can take 9 different values. Mode of the port : ‘0’ , ’1’ , ’L’ , ’H’ , ’Z’ , It can be ’U’ , ’X’ , ’W’ , ’-’ in, out or inout EE705/707 Lecture No. 19 Prof. Maryam Shojaei Baghini
IIT Bombay XOR_gate library IEEE; use IEEE.std_logic_1164.all; architecture architecture_name of entity xor_gate is entity_name is [declarations] generic (p_delay : time:= 2 ns); begin [statements] port (ip1 : in std_logic; ip2 : in std_logic; end [ architecture_name ]; op1 : out std_logic ); The architecture describes the end xor_gate; - behavior of design, - relationship between different inputs and outputs of the entity. - Interconnections between the components architecture xor_gate_beh of xor_gate is (for structural design) begin op1 <= ip1 xor ip2 after p_delay; ‘xor’ is function defined in end xor_gate_beh; std_logic_1164 package. EE705/707 Lecture No. 19 Prof. Maryam Shojaei Baghini
IIT Bombay One more architecture for entity ‘xor_gate’ using internal signals architecture xor_gate_beh1 of xor_gate is signal temp1 : std_logic; signal temp2 : std_logic; begin temp1 <= ip1 and (not ip2) after p_delay ; temp2 <= ip2 and (not ip1) after p_delay; op1 <= temp1 or temp2 after p_delay ; end xor_gate_beh1; EE705/707 Lecture No. 19 Prof. Maryam Shojaei Baghini
IIT Bombay configuration configuration_name of entity_name is for architecture_name for instance_name : component_name use entity library_name.entity_name ( architecture_name ); end for; end for; end configuration_name ; A configuration statement selects one configuration xor_gate_C of xor_gate is of several architectures for a single for xor_gate_beh entity. end for; end xor_gate_C; Components within architectures can also be chosen. configuration xor_gate_C1 of xor_gate is for xor_gate_beh1 Unless specified, the last compiled end for; architecture is used for simulation end xor_gate_C1; EE705/707 Lecture No. 19 Prof. Maryam Shojaei Baghini
IIT Bombay Test Benches. To test a circuit we will design another circuit (test bench) which will generate the signals required to test our circuit. This new circuit is also described in VHDL. XOR_GATE_TS T XOR_GATE ip1 Test op Process 1 ip2 Test Benches should be as simple as possible EE705/707 Lecture No. 19 Prof. Maryam Shojaei Baghini
IIT Bombay entity xor_gate_tst is end xor_gate_tst ; XOR_GATE_TST ip1_s Test XOR_GATE process op1_s ip2_s EE705/707 Lecture No. 19 Prof. Maryam Shojaei Baghini
IIT Bombay entity xor_gate_tst is generic (p_delay_top : time:= 4 ns); end xor_gate_tst; XOR_GATE_TST architecture xor_gate_tst_A of xor_gate_tst is component xor_gate generic (p_delay : time:= 2 ns); ip1_s port (ip1 : in std_logic; ip2 : in std_logic; Test op1 : out std_logic); XOR_GATE end component; process signal ip1_s, ip2_s, op1_s : std_logic; op1_s begin ip2_s U1: xor_gate generic map (p_delay => P_delay_top) port map( ip1 => ip1_s, ip2 => ip2_s, COMPONENT op1 => op1_s ); ........ INSTANTIATIO end xor_gate_tst_A; N EE705/707 Lecture No. 19 Prof. Maryam Shojaei Baghini
IIT Bombay ModelSim Demonstration • Creating Project • Code entry and compilation • Loading the test bench • The object window • Running basic simulation • The wave window • Simulation debugging EE705/707 Lecture No. 19 Prof. Maryam Shojaei Baghini
IIT Bombay REFERENCES 1. IEEE Standard VHDL - Language Reference Manual. 2. VHDL Programming by Example 4th Ed - Douglas Perry. 3. The Designer's Guide to VHDL- Peter J. Ashenden EE705/707 Lecture No. 19 Prof. Maryam Shojaei Baghini
IIT Bombay Thank you EE705/707 Lecture No. 19 Prof. Maryam Shojaei Baghini
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