IITBombay - PowerPoint PPT Presentation

IIT�Bombay ������������������������� IIT�Bombay

IIT�Bombay Slide�1 COURSE�NAME Course�Code: EE705/EE707 Department: Electrical�Engineering Instructor�Name(s):� Maryam�Shojaei�Baghini E�Mail�id : mshojaei@ee.iitb.ac.in

IIT�Bombay Slide�2 Date:�01/09/09��������������������Lecture�No:�10���������������� Lecture:�MAGIC Sub�Topics � Physical�Design�of�Integrated�Circuits�(Layout)4 � MAGIC�Layout�Editor Course:�VLSI�Design�Lab������Lecture�No.�10����Instructor:�M.�Shojaei�Baghini

IIT�Bombay Slide�3 MOSFET � � � � � � � � �� �� �� �� �� �� ������ �� ��������� ����������������������������� Course:�VLSI�Design�Lab������Lecture�No.�10����Instructor:�M.�Shojaei�Baghini

IIT�Bombay Slide�4 Logic�Inverter ������������ !�� Course:�VLSI�Design�Lab������Lecture�No.�10����Instructor:�M.�Shojaei�Baghini

IIT�Bombay Slide�5 Ex.�N�Well�Implant ��������"����� ������ ������ �#�$� ����� ��������� Course:�VLSI�Design�Lab������Lecture�No.�10����Instructor:�M.�Shojaei�Baghini

IIT�Bombay Slide�6 Wires�and�Vias ������� ������� ���� ������� ���� ���� �� �� ����� ���%�������������������� ��&� Course:�VLSI�Design�Lab������Lecture�No.�10���Instructor:�M.�Shojaei�Baghini

IIT�Bombay Slide�7 Ex:�N�Well�Formation One�drawing�layer�(mask)�corresponds�to� several�process�steps.� ����'�(� )�! Course:�VLSI�Design�Lab������Lecture�No.�10����Instructor:�M.�Shojaei�Baghini

IIT�Bombay Slide�8 N�Well�Formation� (Continued)4 ����'�(� )�! Course:�VLSI�Design�Lab������Lecture�No.�10����Instructor:�M.�Shojaei�Baghini

IIT�Bombay Slide�9 N�Well�Formation� (Continued)4 ����'�(� )�! Course:�VLSI�Design�Lab������Lecture�No.�10����Instructor:�M.�Shojaei�Baghini

IIT�Bombay Slide�10 Stick�Diagrams Sizes�need�not�be�scaled. Course:�VLSI�Design�Lab������Lecture�No.�10����Instructor:�M.�Shojaei�Baghini

IIT�Bombay Slide�11 Lambda�Based�Design�Rules Course:�VLSI�Design�Lab������Lecture�No.�10����Instructor:�M.�Shojaei�Baghini

IIT�Bombay Slide�12 Considerations � Layout�Style � Design�and�Electrical�Rules � Geometrical�Design�Rules,�Resolution� � Antenna�Rules � CMP�Rules�(Layer�Density�Rules)4 � Electro�migration�Rules � … Course:�VLSI�Design�Lab������Lecture�No.�10����Instructor:�M.�Shojaei�Baghini

IIT�Bombay Slide�13 Antenna�Rules Long�metal�line�accumulates�charge�during� plasma�etching�which�may�zap�gate�oxide. ����'�(�)*+ �������$� ��&� Course:�VLSI�Design�Lab������Lecture�No.�10����Instructor:�M.�Shojaei�Baghini

IIT�Bombay Slide�14 MAGIC�Layout�Editor� � MAGIC�was�developed�in�Berkeley�in�1980’s � Grid � Pitch�(repeat�distance�between�objects)4 � Examples�of MAGIC�drawing�layers ����'�(�)*+ �������$� ��&� Course:�VLSI�Design�Lab������Lecture�No.�10����Instructor:�M.�Shojaei�Baghini

IIT�Bombay Slide�15 MAGIC�Layout�Editor� (Continued)4 � Technology�File � Rule�Deck�(DRC,�LVS�and�Ext�Rules)4 � TSMC�0.18um�MAGIC�Technology�File Course:�VLSI�Design�Lab������Lecture�No.�10����Instructor:�M.�Shojaei�Baghini