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Variation and Litho-driven Physical Design I SPD 2 0 0 7 Shankar Krishnamoorthy Chief Technical Officer Agenda Physical Design at 65nm/45nm Variation challenges and solutions Routing challenges and solutions Summary 2

  1. Variation and Litho-driven Physical Design I SPD 2 0 0 7 Shankar Krishnamoorthy Chief Technical Officer

  2. Agenda • Physical Design at 65nm/45nm • Variation challenges and solutions • Routing challenges and solutions • Summary 2 Sierra Design Automation, Inc. Confidential

  3. Three Major PD Challenges • Lithography Variations • Complexity in Routing Rules • Need for DFM-driven routing • Process & Operational Variations • Variation-driven STA • Need for Variation-driven implementation • WYSNWYG – 193nm light used to create • Large Design Sizes 65nm/45nm patterns • Due to light dosage, light focus, mask • Scalability of Physical alignment • OPC simulation – exploding data volume Design Algorithms 3 Sierra Design Automation, Inc. Confidential

  4. Agenda • Physical Design at 65nm/45nm • Variation challenges and solutions • Routing challenges and solutions • Summary 4 Sierra Design Automation, Inc. Confidential

  5. Variability Leads to Design Margins DSP, 65nm, 9M Gates, 12 modes/corners RC variation Modes RC variation Modes Voltage Temperature Device (Vt) Variation Voltage Temperature Device (Vt) Variation (maxC, maxVia, (func, pbist, (maxC, maxVia, (func, pbist, (1.08, 1.9) (30, 125) (1.08, 1.9) (30, 125) minC,,minVIA) capture_pll, shift) minC,,minVIA) capture_pll, shift) MARGIN 300ps uncertainty, 12% OCV, 15% RC derate 5 Sierra Design Automation, Inc. Confidential

  6. Design Flow with Margins • Sample Margins MARGIN • 20% faster clock • 250-300ps uncertainty • 10% RC derating Floorplanning LIB Synthesis • 10% OCV Placement • 25% max slew derate LE F CTS Routing Post-Route DRC • Resulting Chips Signoff • 20-100% more time to closure • 5-15% bigger die • 5-15% more power 6 Sierra Design Automation, Inc. Confidential

  7. Design Flow Without Margins • Instead of margins, M1C1 M1C2 M2C1 M3C3 MxCx define mode/corner variation scenarios upfront Floorplanning • Variation Timer back- LIB Synthesis bone ensures closure Placement over each step of flow LEF CTS Routing Post-Route DRC Signoff • Results • Up to 2X faster TAT • Up to 15% smaller die • Up to 15% lesser power 7 Sierra Design Automation, Inc. Confidential

  8. Case Study : Server Chip • Design Details: • 12M gates flat (3M instances) • 4 Corners + 6 Modes (24 Combinations) XAUI (slow_ocv, Cworst) setup, hold BIST (slow_ocv, Cworst) setup, hold XAUI (fast_ocv RCbest) hold, leakage BIST (fast_ocv RCbest) hold, leakage XAUI (fast_lv, Cbest) hold, leakage BIST (fast_lv, Cbest) hold, leakage XAUI (fast_ht, RCworst) hold, leakage BIST (fast_ht, RCworst) hold, leakage RGMII (slow_ocv, Cworst) setup, hold SHFT (slow_ocv, Cworst) setup, hold RGMII (fast_ocv, RCbest) hold, leakage SHFT (fast_ocv, RCbest) hold, leakage RGMII (fast_lv, Cbest) hold, leakage SHFT (fast_lv, Cbest) hold, leakage RGMII (fast_ht, RCworst) hold, leakage SHFT (fast_ht, RCworst) hold, leakage LB (slow_ocv, Cworst) setup, hold CAP (slow_ocv, Cworst) setup, hold LB (fast_ocv, RCbest) hold, leakage CAP (fast_ocv, RCbest) hold, leakage LB (fast_lv, Cbest) hold, leakage CAP (fast_lv, Cbest) hold, leakage LB (fast_ht, RCworst) hold, leakage CAP (fast_ht, RCworst) hold, leakage • Target: • Fix Setup, Hold for All 24 modes/corners • Leakage opt on selected combinations • 14hrs CPU 8 Sierra Design Automation, Inc. Confidential

  9. Key Technologies Needed for Variation aware tools • Concurrent Multi-mode analysis (operational variability) • Concurrent Multi-corner analysis (global variability) • Concurrent local variability analysis (OCV, NBTI, Statistical Models) • Concurrent Multi-mode Multi-corner Implementation • Placement, CTS, Optimization, Routing, DFM Steps • Scalability • Sub-linear increase in runtime and memory with number of scenarios • Hierarchical Methodology • Budgeting, chip-level timing closure are affected by modes and corners 9 Sierra Design Automation, Inc. Confidential

  10. Agenda • Physical Design at 65nm/45nm • Variation challenges and solutions • Routing challenges and solutions • Summary 10 Sierra Design Automation, Inc. Confidential

  11. Routing / OPC interaction At 130/90nm At 65/45nm � OPC analyze/fix iterations take longer Synthesis since routing is oblivious to OPC .lib � Complex DRC rules are developed to prevent bad patterns resulting in longer Placement LEF runtimes / time to closure DRC DRC++ Routing OPC Mask GDSII OPC Routing Complex DRCs 11 Sierra Design Automation, Inc. Confidential

  12. Impact on Routing Rules • Complexity of Routing DRC Rules Increasing • Number of rules increasing from node to node • More rules are becoming dependent on ranges of variables like width, halo, parallel length • Increasing number of objects involved in a rule • Stringent requirements with each node • Recommended or “Soft” Routing Rules increasing in number from node to node, usually for DFM • Routing has to consider Timing and SI constraints • Flexible routing flow and algorithms needed 12 Sierra Design Automation, Inc. Confidential

  13. Migration to shape-based checks S 1 S 2 S 2 S 3 S 1 S 1 Step-Rules Composite shape causes Edge-to-Edge Adding a via causes more different spacing requirements spacing check complicated DRCs to be triggered 13 Sierra Design Automation, Inc. Confidential

  14. Spacing Rules • Between different-nets and same-net objects. • Objects can be port-shapes, wire segments, via metal, pre-routes Metal Parallel Spacing Width Length Range Overlap > L 1 > W 1 S 1 S > L 2 > W 2 S 2 W > L 3 > W 3 S 3 L 14 Sierra Design Automation, Inc. Confidential

  15. Cut Number Rule • Number of vias and spacing between vias when used on “fat” metal OPTIONAL where the second via is placed W>1.7u Number of vias and W>2.4u Spacing between W > 1.7u vias is a parameter 15 Sierra Design Automation, Inc. Confidential

  16. Complex Via Rules • Use double via when turn is less than 5u away from a wide metal • Parameters are length, width and distance from neighbor. Value is number of vias needed W > 3u L>10u Distance < 5u 16 Sierra Design Automation, Inc. Confidential

  17. INFLUENCE Rule S W > 1.7u S Distance of influence All metal connected to fat-metal, inherits the spacing rule of the fat-metal. Also depends upon “distance of influence”. Beyond this distance use standard spacing rules 17 Sierra Design Automation, Inc. Confidential

  18. “Dense” End-of-line Rule for OPC Prevention S 1 L 2 W 1 L 1 • Litho error prevention rule appears in 65nm/45nm nodes 18 Sierra Design Automation, Inc. Confidential

  19. Growing DRC Complexity DRC Rule 130nm 90nm 65nm 45nm Width-based 1-2 2-3 3-5 7 Spacing Min-Area 1pitch 2pitch 3pitch 5pitch Cut Number n.a 1-2 4-5 5-6 Dense End- n.a n.a M1/M2 All layers of-Line (OPC) Min-step n.a 1 5 5 (OPC) 19 Sierra Design Automation, Inc. Confidential

  20. DFM Requirements • Recommended Rules • Via Minimization • Double-via replacement levels • Metal Density Rules • Increase via enclosure where possible • Litho Hot-spot avoidance, detection and repair • Critical Area Analysis (CAA) and CAA-driven wire-spreading for random defect prevention 20 Sierra Design Automation, Inc. Confidential

  21. DFM Metrics DFM Metrics • Via Count • Double Via • Litho HotSpot Counts • CAA score • Metal Density violations With DoubleVia and WireSpreading • Larger via enclosures With WireSpreading 21 Sierra Design Automation, Inc. Confidential

  22. Introduction to Routing Flow • 4 major steps • Global Routing • Computes total resource availability over the chip • Assigns initial topologies to nets • Track Routing • Takes Global Routes as “guides” • Assigns detailed wires on different layers to nets • Detail Routing • Starts with track routing and cleans up DRCs using local routing within small windows • Uses simplified model of complex DRCs for speed • Post-Processing • Cleans up remaining DRC errors with local re-routing in conjunction with DRC checker 22 Sierra Design Automation, Inc. Confidential

  23. Routing Flow : Global Routing Pins to be connected Groute wire GCELL edges on M3 23 Sierra Design Automation, Inc. Confidential

  24. Routing Flow : Track Routing 24 Sierra Design Automation, Inc. Confidential

  25. Routing Flow : Track Routing Target M1 pin is blocked by another net on M2 � short … Via is not clean 25 Sierra Design Automation, Inc. Confidential

  26. Routing Flow : Detail Routing Short resolved Via properly connected 26 Sierra Design Automation, Inc. Confidential

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