Hybrid Controller Chip (HCC) Size: 4700um x 2860um; I/O pads: 83 - PowerPoint PPT Presentation

Hybrid Controller Chip (HCC) • Size: 4700um x 2860um; I/O pads: 83 • Dual pad-ring structure to fit onto Hybrid • IBM Standard Cells: ~20,000 + 727 Decoupling caps (200pF) • Nets: 22,942 • Macros: – Voltage Regulator – Band Gap – PLL /w 40, 80, 160, 320, and 640MHz (Modified GBT ePLL) – Delay Macos: • Synchronous coarse delays (6.25ns steps ) • Asynchronous fine delays (0.6ns steps) • Asynchronous very fine delay (200ps steps) – “Coarse + fine” delays used for Hybrid -side signals (BC_Hybrid, R3sL1, CMDL0) – “fine” delays used for Data Readout Clock (DRC) and returning ABC130 Data – “Very fine” delay used for Phase delay of 640MHz Fast Cluster Finder Clock – Autonomous Monitor (monitors chip health) – Power-on Reset – Prompt event circuit (USA export regulations) • TCL script driven PnR (based on CERN code ) ~ 3600 lines of code • Verification: Verilog, STA (Encounter, Primetime if available), Spectre 3/11/2014 Penn 1

PnR Status • PnR Flow working – LVS clean OA (Virtuoso) database – DRC nearly clean • Some (~10-20) antenna violations , couple spacing. • ECO flow to fix – Timing violations • Analysis of STA constraints continuing • Testbench functional simulations ongoing – Signal Integrity Violations (xtalk glitches) • ECO flow to fix

Liberty files and Constraints Liberty file functions: – Define timing arcs propagated through macros – Define output signal transition rate model – Define pin min/max output capacitances for modeling edge rates – Define pin input max_transition rate (limit of tables) • ePLL and AutonMon do not require one for timing purposes however: • Still need Liberty file for output transition model and capacitances • Can we use clock constraints instead?? (set_clock_transition, set_input_delay, etc) – All input/output pads have liberty files to time arcs w.r.t. external signals (virtual external clock) • Delay elements only need combinatorial logic delays defined when select lines are set to minimum. (created by encounter during macro PnR) – Still missing Pre-emphasis driver Liberty file for GBT.

Power/Ground connections Spectre simulation • Removed synthesized core logic • Keep all macros (ePLL, Delay elements) • Ramp up raw DVDD voltage • Watch Regulator and Bandgap work – Schematic sim after LVS – Next, extracted netlist sim

HCC Clock Domains: BC_STAVE, ePLL f A, ePLL f 1, LOCAL40/80/160, Fclk BCdelayC<1:0> ePLL BCdelayF<3:0> BC_STAVE REF IN 2 4 BC BC_HYBRID 640MHz Coarse Fine RCVR 320MHz 160MHz (40 MHz) Delay Delay Trigger_gen_rst f 1 PIO_DRV160 f A MACRO PIO_REC160 R3sL1delayC<1:0> (NO hysteresis on clocks) Fclk R3sL1delayF<3:0> R3 2 4 R3_L1 R3sL1_HYBRID dmux Coarse Fine L1 R3sL1 Rcvr (80 MBS) Delay Delay PIO_DRV160 MACRO PIO_HYSTREC CMDL0delayC<1:0> CMDL0delayF<3:0> L0_CMD L0 2 4 CMDL0_HYBRID Coarse Fine Rcvr dmux (80 MBS) Delay Delay CMD rst PIO_DRV160 MACRO PIO_HYSTREC DIVIDE 2 Rclk_HYBRID * (80/160 MHz) rst 40MHz COMMAND (160 MHz) PIO_DRV160 (80 MHz) * Clock speed options: DECODER DataXdelayF<3:0> Static/analog 80 or 160 MHz Sel_Rclk X = 1,2,3,4 X 4 (80/160 MHz) Fine Delay 80MHz or f1 Data MACRO MACRO 320 MHz Point-to -Point f A X 160 MHz 640 MHz (Fclk) 4 Data to GBT (80/160 MHz) Fine Delay Data (8b/10b encoded) 80 MHz 320MHz (80/160 MHz) Sel_FCF MACRO FCFdelayC<3:0> Xoff out X 320 MHz Data 4 (80/160 MHz) FDELAY Data Data 4 Fine Delay Drivers (DelayLine) Data in MACRO Concentrator PIO_PRE_EMPH PIO_DRV160 640MHz X 640MHz Fclk 4 (80/160 MHz) Data Fine Delay MUX21BAL_L 320MHz ( f A) MACRO 160MHz ( f 1) 3/12/2014 5 PIO_REC160

How to delay BC_HYBRID ? (Coarse Delay using Shift register + Fine Delay using Delay Line) • Coarse Delay : Done with shift register driven by 160MHz clock. • 6.25ns steps, ( NO RESET ISSUES ) • Fine Delay : tapped delay chain • 420 to 830 ps PVT range; step size using 16-Tap Delay Line) ePLL BC_STAVE ref Fine Delay 40MHz 160MHz (16 Taps) Select fine Delay f1 4 BC_HYBRID Asynchronous Fine Delay: 40MHz • Min step size: 420 ps (T= - 30C) • Max step size: 830 ps (T=55C) N=2 ? (4 Taps) Select Coarse Delay Output Coarse Delay N bit MUX Input Tap1 Tap2 Tap3 TapN D Q D Q D Q D Q D Q f1 160 MHz 6.25 ns /tap Here is how to avoid startup phase issues on BC_HYBRID clock: • Directly delay BC_STAVE using shift register • ePLL guantees a known (programmable) relationship between BC_STAVE and f1 • Any jitter on BC_STAVE is eliminated when the (stable) ePLL f1 clock samples it. 3/12/2014 6