Hardware description and verification Getting hardware designs right [using ideas from computer science]
TECHNICAL VHDL PSL Gaisler’s 2 process method Writing VHDL code CTL (LTL) .... PSL circuit properties Writing and reading PSL properties The flow you have used (your opinions) CTL semantics JasperGold transition system from netlist (circuit) (will put examples in written form up) CTL model checking YES or trace of bug BDDS and their role (advantages and disadv.) Fixed point iteration in concrete examples
BACKGROUND KNOWLEGE VHDL PSL Verification beginning to dominate development cost (cf. ITRS) The idea that expressiveness and ease of proof have to be traded off against each other circuit properties The importance of automation FV remains a complement to simulation (see talk about verif. at IBM) Mixing sim. and FV now hot JasperGold (called semi-formal, cf. IBM Sixth Sense) There are other spec. Langs include SVA (System Verilog Assertions) YES or trace of bug
TECHNICAL How to write small Lava descriptions Lava and properties Properties as observers notion of a safety property circuit generator properties Use of recursion in structural cct desc. (examples and answers in LT see exercises 5.1 to 5.10) Lava Advantages and disadvantages Where it fits in a standard approach YES or NO SAT-based verification temporal induction
BACKGROUND (languages) Two level language (generators), domain specific embedded language Patterns for verification and not just for circuits would be useful Need *both* to take account of low level physical details *and* raise level of abstraction at which design is done! Wired attempts to address a small version of this problem Martin’s HDML (IBM) will attempt to address this problem in open source project (see later)
BACKGROUND (languages) Use of functional languages in hardware design and verification at Intel. IDV very interesting (seeing use in real datapath design) But it is not clear if there are real openings in large companies for non-standard languages However, look at Mitrionics AB! In the mainstream, System Verilog looks to be winning Note Bluespec SV To follow the mainstream, read Deepchip and EETimes
BACKGROUND (verification) Need for hierarchy (Assume Guarantee reasoning, environment models) Commercial formal tools based on a variety of methods (BDD-based MC, BMC, induction, CEGAR, ...) Scalability of underlying algorithms still a major issue (and research problem) Verification of embedded software combined with hardware is a current hot topic, but note that HARDWARE VERIFICATION IS NOT A SOLVED PROBLEM (see interesting talks on FMCAD 2006 website)
Feedback Please give feedback about the course to Kasyab and Junaid (or of course to me directly). There will be a web based questionnaire as part of the Chalmers eval. Process So how would you have the course if you were suddenly in charge of it for next year??
Masters thesis project topics Using Lava or Wired to design and analyse X can have emphasis on Lava/Wired or on X X is typically at the level of adder or multiplier but we are open to suggestions Example might be to study sorter design. (There are some very interesting papers from the 70s that could be mined for good ideas.) Second example (suggested by Per LE) is to investigate the effect of going down through process nodes on (say) parallel prefix networks (using Wired)
Masters thesis project topics Related to HDML (with IBM Research, Austin) 1) Case studies ” Simply expressing stuff in HDML is useful. It’s a new format for expressing hardware designs. One could use many different styles to accomplish the same thing. Still don’t know what the ”right” way to express things is.”
Masters thesis project topics Related to HDML (with IBM Research, Austin) 2) Abstraction on top of HDML ”Can one design a higher-level design framework on top of the existing HDML language. For example: correct by construction pipelining or elastic pipelines in the style of . Kristic, Cortadella and Kishinevsky ”
Masters thesis project topics Related to HDML (with IBM Research, Austin) 3) What would HDML look like if it was built on top of Meta- Ocaml? ” Reimplement HDML simulation kernel in Meta-Ocaml Can the existing fixed-width library be subsumed by the resource bounded features of Meta-Ocaml ?” [ I’m not sure I can supervise this, but I could probably get the Meta-Ocaml guy to help.] 4) … There are several more projects for expert functional programmers
Masters thesis project topics Using a standard flow (VHDL+PSL) to design and analyse an X (Supervisor has to know something about X) Concrete example from Saab Space (to be done there) Development of TCP/IP in VHDL description in Swedish :( on links page tonight, including email address for application. See me if you are interested and need a translation. Deadline May 31. Note also that Jasper plan to suggest a project
Masters thesis project topics Development of a domain specific language for DSP algorithm design (project with Ericsson and Galois, Inc.) Initial case studies. Look at www.cryptol.net GPU programming!
Recommend
More recommend
