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Introduction TLM RTC Abstract Interpretation Conclusion Habilitation Diriger des Recherches High-level Models for Embedded Systems Matthieu Moy Verimag (Grenoble INP) Grenoble, France March 13 th 2014 Jury: Grard Berry Professeur au

  1. Introduction TLM RTC Abstract Interpretation Conclusion Issue 4: Power and Temperature 20 watt 50-130 watt < 1 watt 20-30 watt March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 10 / 51 >

  2. Introduction TLM RTC Abstract Interpretation Conclusion Issue 5: Simulation speed March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 11 / 51 >

  3. Introduction TLM RTC Abstract Interpretation Conclusion Issue 6: Model Faithfulness model actual Unmodeled behaviors (B) Extra behaviors of the model (A) Exactly modeled behaviors (C) March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 12 / 51 >

  4. Introduction TLM RTC Abstract Interpretation Conclusion Models and Virtual Prototypes Model/Prototype Real system March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 13 / 51 >

  5. Introduction TLM RTC Abstract Interpretation Conclusion Models and Virtual Prototypes Synthesize Model/Prototype Real system March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 13 / 51 >

  6. Introduction TLM RTC Abstract Interpretation Conclusion Models and Virtual Prototypes (Synthesize) Model/Prototype Real system March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 13 / 51 >

  7. Introduction TLM RTC Abstract Interpretation Conclusion Models and Virtual Prototypes (Synthesize) Compare Use as specification ... Model/Prototype Real system March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 13 / 51 >

  8. Introduction TLM RTC Abstract Interpretation Conclusion Context and Collaborations of my Work 2002 2005 2010 2014 My Ph.D G. Funchal Ph.D OpenTLM OpenES FoToVP HELP CESyMPA Combest

  9. Introduction TLM RTC Abstract Interpretation Conclusion Context and Collaborations of my Work STMicroelectronics 2002 2005 2010 2014 My Ph.D G. Funchal Ph.D OpenTLM OpenES FoToVP HELP CESyMPA Combest

  10. Introduction TLM RTC Abstract Interpretation Conclusion Context and Collaborations of my Work STMicroelectronics 2002 2005 2010 2014 My Ph.D G. Funchal Ph.D OpenTLM OpenES FoToVP HELP CESyMPA Combest CEA-LETI TIMA Docea IRISA Power INRIA Rhone ETHZ Alpes March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 14 / 51 >

  11. Introduction TLM RTC Abstract Interpretation Conclusion Outline Abstract Real-Time Interpretation Calculus SystemC/TLM March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 15 / 51 >

  12. Introduction TLM RTC Abstract Interpretation Conclusion Outline Abstract Real-Time Interpretation Calculus SystemC/TLM March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 15 / 51 >

  13. Introduction TLM RTC Abstract Interpretation Conclusion TLM and Software Development Traditional Model based Design-Flow Specification, Specification, Algorithm Algorithm Model RTL Design RTL Design Software Development Synthesis Synthesis Time Integration Factory Factory Software Development Validation Integration gain Validation March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 16 / 51 >

  14. Introduction TLM RTC Abstract Interpretation Conclusion TLM and Software Development Traditional Model based Design-Flow Specification, Specification, Algorithm Algorithm TLM Model RTL Design RTL Design Software Development Synthesis Synthesis Time Integration Factory Factory Software Development Validation Integration gain Validation March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 16 / 51 >

  15. Introduction TLM RTC Abstract Interpretation Conclusion The Transaction Level Model (TLM): Principles and Objectives A high level of abstraction, that appears early in the design-flow March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 17 / 51 >

  16. Introduction TLM RTC Abstract Interpretation Conclusion The Transaction Level Model (TLM): Principles and Objectives A high level of abstraction, that appears early in the design-flow ≈ 1000 Faster than low-level simulations (RTL) March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 17 / 51 >

  17. Introduction TLM RTC Abstract Interpretation Conclusion The Transaction Level Model (TLM): Principles and Objectives A high level of abstraction, that appears early in the design-flow ≈ 1000 Faster than low-level simulations (RTL) In production in the industry March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 17 / 51 >

  18. Introduction TLM RTC Abstract Interpretation Conclusion Content of a TLM Model Model what is needed for read write Software Execution: - addr - addr ◮ Processors - data - data ◮ Address-map ◮ Concurrency ... and only that. ◮ No micro-architecture ◮ No bus protocol ◮ No pipeline ◮ No physical clock addr ◮ . . . data Standard for TLM = SystemC (IEEE1666) March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 18 / 51 >

  19. Introduction TLM RTC Abstract Interpretation Conclusion An Example TLM Model CPU ITC VGA Timer process = C++ code TLM Bus Data RAM Instruction RAM GPIO March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 19 / 51 >

  20. Introduction TLM RTC Abstract Interpretation Conclusion Uses of Functional Models SPEC Reference for Hardware Validation Virtual Prototype for Software Development March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 20 / 51 >

  21. Introduction TLM RTC Abstract Interpretation Conclusion Uses of Functional Models SPEC Reference for RTL ? Hardware = Validation Virtual Prototype for Software Development March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 20 / 51 >

  22. Introduction TLM RTC Abstract Interpretation Conclusion Uses of Functional Models SPEC Reference for CPU RTL TLM process = ITC VGA Timer ? C++ code Hardware = TLM Bus Validation Data RAM Instruction RAM GPIO Virtual Prototype for Software Development March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 20 / 51 >

  23. Introduction TLM RTC Abstract Interpretation Conclusion Uses of Functional Models SPEC Reference for CPU RTL TLM process = ITC VGA Timer ? C++ code Hardware = TLM Bus Validation Data RAM Instruction RAM GPIO Virtual Prototype for Software CPU TLM ITC VGA Timer process = Development C++ code TLM Bus Data RAM Instruction RAM GPIO March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 20 / 51 >

  24. Introduction TLM RTC Abstract Interpretation Conclusion Uses of Functional Models SPEC Reference for CPU RTL TLM process = ITC VGA Timer ? C++ code Hardware = TLM Bus Validation Data RAM Instruction RAM GPIO Unmodified Software Virtual Prototype for Software CPU TLM ITC VGA Timer process = Development C++ code TLM Bus Data RAM Instruction RAM GPIO March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 20 / 51 >

  25. Introduction TLM RTC Abstract Interpretation Conclusion Non-Functional Models Timing, Power consumption, Temperature Estimation CPU TLM process = ITC VGA Timer C++ code TLM Bus Data RAM Instruction RAM GPIO March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 21 / 51 >

  26. Introduction TLM RTC Abstract Interpretation Conclusion Non-Functional Models Timing, Power consumption, Temperature Estimation CPU TLM process = ITC VGA Timer C++ code TLM Bus Data RAM Instruction RAM GPIO 60 60 50 50 40 40 30 30 20 20 10 10 0 0 10 10 20 20 30 30 Estimated Actual Time/Power/Temperature March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 21 / 51 >

  27. Introduction TLM RTC Abstract Interpretation Conclusion Non-Functional Models Timing, Power consumption, Temperature Estimation Unmodified Power/Temperature-Aware Software CPU TLM process = ITC VGA Timer C++ code TLM Bus Data RAM Instruction RAM GPIO 60 60 50 50 40 40 30 30 20 20 10 10 0 0 10 10 20 20 30 30 Estimated Actual Time/Power/Temperature March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 21 / 51 >

  28. Introduction TLM RTC Abstract Interpretation Conclusion Contributions on TLM Simulation Speed Early Software Execution Timing Faithfulness Power/Temperature Correctness March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 22 / 51 >

  29. Introduction TLM RTC Abstract Interpretation Conclusion Contributions on TLM Simulation Speed Optimizing Compiler Early Software Execution Parallelization Compilation Smart FIFO Memory Models jTLM Timing Faithfulness Formal Traffic models Verification Power/Temperature Functional/extra-functional Correctness Cosimulation March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 22 / 51 >

  30. Introduction TLM RTC Abstract Interpretation Conclusion Contributions on TLM Simulation Speed Optimizing Compiler Early Software Execution Parallelization Compilation Smart FIFO Memory Models jTLM Timing Faithfulness Formal Traffic models Verification Power/Temperature Functional/extra-functional Correctness Cosimulation March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 22 / 51 >

  31. Introduction TLM RTC Abstract Interpretation Conclusion SystemC: Simple Example A B int sc_main (int, char **) { struct A : sc_module { /* Instanciate modules */ /* Connection to outside */ A a("Alice"); initiator_socket socket; B b("Bob"); /* Behavior */ /* Connect them together */ void thread() { a.socket.bind(b.socket); do_stuff(); write(socket, addr, data); /* and start simulation */ } sc_start(); return 0; SC_CTOR(A) { } SC_THREAD(thread); } }; � Compilable with any C++ compiler March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 23 / 51 >

  32. Introduction TLM RTC Abstract Interpretation Conclusion Challenges and Solutions with SystemC Front-Ends C++ is complex (e.g. clang++ ≈ 400,000 LOC) 1 Architecture built at runtime, with C++ code 2 int sc_main (int, char **) { struct A : sc_module { /* Instanciate modules */ /* Connection to outside */ A a("Alice"); initiator_socket socket; B b("Bob"); /* Behavior */ /* Connect them together */ void thread() { a.socket.bind(b.socket); do_stuff(); write(socket, addr, data); /* and start simulation */ } sc_start(); return 0; SC_CTOR(A) { } SC_THREAD(thread); } }; Kevin Marquet Guillaume Sergent March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 24 / 51 >

  33. Introduction TLM RTC Abstract Interpretation Conclusion Challenges and Solutions with SystemC Front-Ends C++ is complex (e.g. clang++ ≈ 400,000 LOC) 1 � Write a C++ front-end or reuse one (g++, clang++, EDG, . . . ) Architecture built at runtime, with C++ code 2 � Analyze elaboration phase or execute it int sc_main (int, char **) { struct A : sc_module { /* Instanciate modules */ /* Connection to outside */ A a("Alice"); initiator_socket socket; B b("Bob"); /* Behavior */ /* Connect them together */ void thread() { a.socket.bind(b.socket); do_stuff(); write(socket, addr, data); /* and start simulation */ } sc_start(); return 0; SC_CTOR(A) { } SC_THREAD(thread); } }; Kevin Marquet Guillaume Sergent March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 24 / 51 >

  34. Introduction TLM RTC Abstract Interpretation Conclusion Challenges and Solutions with SystemC Front-Ends C++ is complex (e.g. clang++ ≈ 400,000 LOC) 1 � Write a C++ front-end or reuse one (g++, clang++, EDG, . . . ) Architecture built at runtime, with C++ code 2 � Analyze elaboration phase or execute it int sc_main (int, char **) { struct A : sc_module { /* Instanciate modules */ /* Connection to outside */ A a("Alice"); initiator_socket socket; Dynamic B b("Bob"); /* Behavior */ Approaches /* Connect them together */ void thread() { Static a.socket.bind(b.socket); do_stuff(); write(socket, addr, data); Approaches /* and start simulation */ } sc_start(); return 0; SC_CTOR(A) { } SC_THREAD(thread); } }; Kevin Marquet Guillaume Sergent March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 24 / 51 >

  35. Introduction TLM RTC Abstract Interpretation Conclusion Contributions on TLM Simulation Speed Optimizing Compiler Early Software Execution Parallelization Compilation Smart FIFO Memory Models jTLM Timing Faithfulness Formal Traffic models Verification Power/Temperature Functional/extra-functional Correctness Cosimulation March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 25 / 51 >

  36. Introduction TLM RTC Abstract Interpretation Conclusion Contributions on TLM Simulation Speed Optimizing Compiler Early Software Execution Parallelization Compilation Smart FIFO Memory Models jTLM Timing Faithfulness Formal Traffic models Verification Power/Temperature Functional/extra-functional Correctness Cosimulation March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 25 / 51 >

  37. Introduction TLM RTC Abstract Interpretation Conclusion Formal Verification: Encoding Approaches SystemC program Built-in Property Encoding knowledge of SystemC Formal language Lesar, Nbac (Lustre) Existing SMV verifier SPIN (Promela) Yes/No/Maybe Kevin Marquet March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 26 / 51 >

  38. Introduction TLM RTC Abstract Interpretation Conclusion Contributions on TLM Simulation Speed Optimizing Compiler Early Software Execution Parallelization Compilation Smart FIFO Memory Models jTLM Timing Faithfulness Formal Traffic models Verification Power/Temperature Functional/extra-functional Correctness Cosimulation March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 27 / 51 >

  39. Introduction TLM RTC Abstract Interpretation Conclusion Contributions on TLM Simulation Speed Optimizing Compiler Early Software Execution Parallelization Compilation Smart FIFO Memory Models jTLM Timing Faithfulness Formal Traffic models Giovanni Funchal Verification Power/Temperature Functional/extra-functional Correctness Cosimulation March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 27 / 51 >

  40. Introduction TLM RTC Abstract Interpretation Conclusion Contributions on TLM Simulation Speed Optimizing Compiler Early Software Execution Parallelization Compilation Smart FIFO Memory Models jTLM Timing Faithfulness Formal Traffic models Giovanni Funchal Nabila Abdessaied Verification Power/Temperature Functional/extra-functional Correctness Cosimulation March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 27 / 51 >

  41. Introduction TLM RTC Abstract Interpretation Conclusion Contributions on TLM Simulation Speed Optimizing Compiler Early Software Execution Parallelization Compilation Smart FIFO Memory Models jTLM Timing Faithfulness Formal Traffic models Verification Power/Temperature Functional/extra-functional Correctness Cosimulation March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 27 / 51 >

  42. Introduction TLM RTC Abstract Interpretation Conclusion Simulation Parallelization March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 28 / 51 >

  43. Introduction TLM RTC Abstract Interpretation Conclusion Simulation Parallelization SystemC uses co-routine semantics (Sequential) March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 28 / 51 >

  44. Introduction TLM RTC Abstract Interpretation Conclusion Problems and Solutions for Parallel Execution of SystemC/TLM (1) Execution order imposed by SystemC (2) Race conditions (e.g. x++ on global variable) March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 29 / 51 >

  45. Introduction TLM RTC Abstract Interpretation Conclusion Problems and Solutions for Parallel Execution of SystemC/TLM (1) Execution order imposed by SystemC (2) Race conditions (e.g. x++ on global variable) � No efficient and automatic solution for SystemC/TLM March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 29 / 51 >

  46. Introduction TLM RTC Abstract Interpretation Conclusion Problems and Solutions for Parallel Execution of SystemC/TLM (1) Execution order imposed by SystemC (2) Race conditions (e.g. x++ on global variable) � No efficient and automatic solution for SystemC/TLM Our proposal = new constructs: Desynchronisation (1) / Synchronisation (2) March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 29 / 51 >

  47. Introduction TLM RTC Abstract Interpretation Conclusion SC - DURING : The Idea SC_THREAD_1 OS thread_1 SC_THREAD_2 OS thread_2 . . . SC_THREAD_N OS thread_ N SystemC OS Thread Unmodified SystemC Computations delegated to external threads Weak synchronization between SystemC and tasks with duration March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 30 / 51 >

  48. Introduction TLM RTC Abstract Interpretation Conclusion Simulated Time in SystemC and SC - DURING SystemC A B SC - DURING P Q March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 31 / 51 >

  49. Introduction TLM RTC Abstract Interpretation Conclusion Simulated Time in SystemC and SC - DURING f() Process A: wait(20) // computation SystemC A f(); // time taken by f B wait(20, SC_NS); SC - DURING P Q March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 31 / 51 >

  50. Introduction TLM RTC Abstract Interpretation Conclusion Simulated Time in SystemC and SC - DURING f() Process A: wait(20) // computation SystemC A f(); // time taken by f B wait(20, SC_NS); g() Process P: wait(20) SC - DURING g(); P wait(20, SC_NS); Q March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 31 / 51 >

  51. Introduction TLM RTC Abstract Interpretation Conclusion Simulated Time in SystemC and SC - DURING f() Process A: wait(20) // computation SystemC A f(); // time taken by f B wait(20, SC_NS); g() Process P: wait(20) SC - DURING g(); h() P wait(20, SC_NS); during(15, SC_NS, h); Q March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 31 / 51 >

  52. Introduction TLM RTC Abstract Interpretation Conclusion Simulated Time in SystemC and SC - DURING f() Process A: wait(20) // computation SystemC A f(); // time taken by f B wait(20, SC_NS); g() Process P: wait(20) SC - DURING g(); h() P wait(20, SC_NS); during(15, SC_NS, h); i() j() Q March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 31 / 51 >

  53. Introduction TLM RTC Abstract Interpretation Conclusion SC - DURING : Sketch of Implementation void during(sc_core::sc_time d, std::function<void()> f) { 1 std::thread t(f); // Create thread sc_core::wait(d); // SystemC executes 2 3 t.join(); // Wait for completion } A B C Thread March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 32 / 51 >

  54. Introduction TLM RTC Abstract Interpretation Conclusion SC - DURING : Sketch of Implementation void during(sc_core::sc_time d, std::function<void()> f) { 1 std::thread t(f); // Create thread sc_core::wait(d); // SystemC executes 2 3 t.join(); // Wait for completion } during(d, f); A B C Thread March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 32 / 51 >

  55. Introduction TLM RTC Abstract Interpretation Conclusion SC - DURING : Sketch of Implementation void during(sc_core::sc_time d, std::function<void()> f) { 1 std::thread t(f); // Create thread sc_core::wait(d); // SystemC executes 2 3 t.join(); // Wait for completion } during(d, f); A B C 1 create thread Thread f March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 32 / 51 >

  56. Introduction TLM RTC Abstract Interpretation Conclusion SC - DURING : Sketch of Implementation void during(sc_core::sc_time d, std::function<void()> f) { 1 std::thread t(f); // Create thread sc_core::wait(d); // SystemC executes 2 3 t.join(); // Wait for completion } during(d, f); A B C 1 2 wait(d) create thread Thread f March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 32 / 51 >

  57. Introduction TLM RTC Abstract Interpretation Conclusion SC - DURING : Sketch of Implementation void during(sc_core::sc_time d, std::function<void()> f) { 1 std::thread t(f); // Create thread sc_core::wait(d); // SystemC executes 2 3 t.join(); // Wait for completion } during(d, f); A B C 1 2 wait(d) create thread Thread f March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 32 / 51 >

  58. Introduction TLM RTC Abstract Interpretation Conclusion SC - DURING : Sketch of Implementation void during(sc_core::sc_time d, std::function<void()> f) { 1 std::thread t(f); // Create thread sc_core::wait(d); // SystemC executes 2 3 t.join(); // Wait for completion } during(d, f); A B C 1 3 2 wait(d) create join() thread Thread f March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 32 / 51 >

  59. Introduction TLM RTC Abstract Interpretation Conclusion SC - DURING : Sketch of Implementation void during(sc_core::sc_time d, std::function<void()> f) { 1 std::thread t(f); // Create thread sc_core::wait(d); // SystemC executes 2 3 t.join(); // Wait for completion } during(d, f); A B C 1 3 2 wait(d) create join() thread Thread f March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 32 / 51 >

  60. Introduction TLM RTC Abstract Interpretation Conclusion SC - DURING : Sketch of Implementation void during(sc_core::sc_time d, std::function<void()> f) { 1 std::thread t(f); // Create thread + thread pooling sc_core::wait(d); // SystemC executes 2 3 t.join(); // Wait for completion } during(d, f); A B + richer C 1 3 synchronization API 2 wait(d) create join() thread Thread f March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 32 / 51 >

  61. Introduction TLM RTC Abstract Interpretation Conclusion SC - DURING : Results 14 Loosely-Timed Models 12 10 Speedup 8 6 4 Fine-grain Timing 2 Number of CPUs in the platform 0 10 20 30 40 50 60 Swadhin Mangaraj Test machine has 4 × 12 = 48 cores March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 33 / 51 >

  62. Introduction TLM RTC Abstract Interpretation Conclusion Contributions on TLM Simulation Speed Optimizing Compiler Early Software Execution Parallelization Compilation Smart FIFO Memory Models jTLM Timing Faithfulness Formal Traffic models Verification Power/Temperature Functional/extra-functional Correctness Cosimulation March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 34 / 51 >

  63. Introduction TLM RTC Abstract Interpretation Conclusion Contributions on TLM Simulation Speed Optimizing Compiler Early Software Execution Parallelization Compilation Smart FIFO Memory Models Samuel Jones jTLM Timing Faithfulness Formal Traffic models Verification Power/Temperature Functional/extra-functional Correctness Cosimulation March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 34 / 51 >

  64. Introduction TLM RTC Abstract Interpretation Conclusion Contributions on TLM Simulation Speed Optimizing Compiler Early Software Execution Parallelization Compilation Smart FIFO Memory Models jTLM Timing Faithfulness Formal Traffic models Verification Power/Temperature Functional/extra-functional Correctness Cosimulation March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 34 / 51 >

  65. Introduction TLM RTC Abstract Interpretation Conclusion SystemC and Extra-Functional Solver Cosimulation Power States Power and Temperature SystemC Solver (ATMI, ACEplorer) Temperature March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 35 / 51 >

  66. Introduction TLM RTC Abstract Interpretation Conclusion SystemC and Extra-Functional Solver Cosimulation Power States Power and Temperature SystemC Solver (ATMI, ACEplorer) Temperature Tayeb Bouhadiba Claude Helmstetter March 13 th 2014 Matthieu Moy (Verimag) High-level Models for Embedded Systems < 35 / 51 >

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