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Packaging for Power Electronics Habilitation Diriger des Recherches Cyril B UTTAY Laboratoire Ampre, Lyon, France 2015 1 / 45 Outline Professional Record Background Contributions Perspectives Conclusion 1 / 45 Outline

  1. High temperature behaviour of SiC devices Thermal Run-away mechanism ◮ The device characteristic ◮ Its associated cooling system ◮ Two equilibrium points: one stable and one unstable ◮ Above the unstable point, run-away occurs 14 / 45

  2. High temperature behaviour of SiC devices Thermal Run-away mechanism ◮ The device characteristic ◮ Its associated cooling system ◮ Two equilibrium points: one stable and one unstable ◮ Above the unstable point, run-away occurs 14 / 45

  3. High temperature behaviour of SiC devices Thermal Run-away mechanism ◮ The device characteristic ◮ Its associated cooling system ◮ Two equilibrium points: one stable and one unstable ◮ Above the unstable point, run-away occurs 14 / 45

  4. High temperature behaviour of SiC devices Thermal Run-away mechanism ◮ The device characteristic ◮ Its associated cooling system ◮ Two equilibrium points: one stable and one unstable ◮ Above the unstable point, run-away occurs 14 / 45

  5. High temperature behaviour of SiC devices Thermal Run-away mechanism ◮ The device characteristic ◮ Its associated cooling system ◮ Two equilibrium points: one stable and one unstable ◮ Above the unstable point, run-away occurs Always stable 14 / 45

  6. High temperature behaviour of SiC devices Thermal Run-away mechanism ◮ The device characteristic ◮ Its associated cooling system ◮ Two equilibrium points: one stable and one unstable ◮ Above the unstable point, run-away occurs Always stable Always unstable 14 / 45

  7. High temperature behaviour of SiC devices Thermal Run-away mechanism ◮ The device characteristic ◮ Its associated cooling system ◮ Two equilibrium points: one stable and one unstable ◮ Above the unstable point, run-away occurs Always stable Always unstable Becomming unstable with ambient temperature rise 14 / 45

  8. Power dissipation as a function of the junction temp. 140 2.0 A 4.0 A 120 6.0 A Dissipated power [W] 8.0 A 100 10.0 A 80 60 40 20 0 50 0 50 100 150 200 250 300 Junction temperature [C] 15 / 45

  9. Power dissipation as a function of the junction temp. 1K/W 140 2.0 A 4.0 A 120 6.0 A Dissipated power [W] 8.0 A 100 10.0 A 2K/W 80 60 4.5K/W 40 20 0 50 0 50 100 150 200 250 300 Junction temperature [C] 15 / 45

  10. High Temperature Thermal Management Buttay et al. “Thermal Stability of Silicon Carbide Power JFETs”, IEEE Trans on Electron Devices, 2014 80 70 SiC JFET: Run-away ◮ 490 m Ω , 1200 V 60 power [W] ◮ R Th JA = 4 . 5 K / W 50 ◮ 135 ° C ambient ◮ On-state losses 40 current changed from 3.65 to 3.7 A 30 100 150 200 250 300 350 time [s] High temperature capability � = reduced cooling needs! SiC JFETs must be attached to a low- R Th cooling system. 16 / 45

  11. High Temperature die attaches The problem with solders Solders operate in Homologous temperature: this region Strengh/Hardness T H = T Oper [ K ] Properties little Unable to bear a ff ected by engineering T Melt [ K ] temperature Creep range loads Example: ◮ AuGe solder: T Melt = 356° C = 629 K 0 0.4 0.6 1 ◮ T H = 0 . 8 ➜ T Oper = 503 K = 230 ° C Homologous Temperature Source: ❤tt♣✿✴✴✇✇✇✳❛♠✐✳❛❝✳✉❦✴❝♦✉rs❡s✴t♦♣✐❝s✴✵✶✻✹❴❤♦♠t✴ ◮ High temperature solder alloys not practical ◮ Need to decorrelate process temperature and melting point: ◮ Sintering (solid state, process below melting point) ◮ Diffusion soldering/TLPB (creation of a high melting point alloy) 17 / 45

  12. High Temperature die attaches The problem with solders Solders operate in Homologous temperature: this region Strengh/Hardness T H = T Oper [ K ] Properties little Unable to bear a ff ected by engineering T Melt [ K ] temperature Creep range loads Example: ◮ AuGe solder: T Melt = 356° C = 629 K 0 0.4 0.6 1 ◮ T H = 0 . 8 ➜ T Oper = 503 K = 230 ° C Homologous Temperature Source: ❤tt♣✿✴✴✇✇✇✳❛♠✐✳❛❝✳✉❦✴❝♦✉rs❡s✴t♦♣✐❝s✴✵✶✻✹❴❤♦♠t✴ ◮ High temperature solder alloys not practical ◮ Need to decorrelate process temperature and melting point: ◮ Sintering (solid state, process below melting point) ◮ Diffusion soldering/TLPB (creation of a high melting point alloy) 17 / 45

  13. High Temperature die attaches The problem with solders Solders operate in Homologous temperature: this region Strengh/Hardness T H = T Oper [ K ] Properties little Unable to bear a ff ected by engineering T Melt [ K ] temperature Creep range loads Example: ◮ AuGe solder: T Melt = 356° C = 629 K 0 0.4 0.6 1 ◮ T H = 0 . 8 ➜ T Oper = 503 K = 230 ° C Homologous Temperature Source: ❤tt♣✿✴✴✇✇✇✳❛♠✐✳❛❝✳✉❦✴❝♦✉rs❡s✴t♦♣✐❝s✴✵✶✻✹❴❤♦♠t✴ ◮ High temperature solder alloys not practical ◮ Need to decorrelate process temperature and melting point: ◮ Sintering (solid state, process below melting point) ◮ Diffusion soldering/TLPB (creation of a high melting point alloy) 17 / 45

  14. High Temperature die attaches The problem with solders Solders operate in Homologous temperature: this region Strengh/Hardness T H = T Oper [ K ] Properties little Unable to bear a ff ected by engineering T Melt [ K ] temperature Creep range loads Example: ◮ AuGe solder: T Melt = 356° C = 629 K 0 0.4 0.6 1 ◮ T H = 0 . 8 ➜ T Oper = 503 K = 230 ° C Homologous Temperature Source: ❤tt♣✿✴✴✇✇✇✳❛♠✐✳❛❝✳✉❦✴❝♦✉rs❡s✴t♦♣✐❝s✴✵✶✻✹❴❤♦♠t✴ ◮ High temperature solder alloys not practical ◮ Need to decorrelate process temperature and melting point: ◮ Sintering (solid state, process below melting point) ◮ Diffusion soldering/TLPB (creation of a high melting point alloy) 17 / 45

  15. High Temperature die attaches The problem with solders Solders operate in Homologous temperature: this region Strengh/Hardness T H = T Oper [ K ] Properties little Unable to bear a ff ected by engineering T Melt [ K ] temperature Creep range loads Example: ◮ AuGe solder: T Melt = 356° C = 629 K 0 0.4 0.6 1 ◮ T H = 0 . 8 ➜ T Oper = 503 K = 230 ° C Homologous Temperature Source: ❤tt♣✿✴✴✇✇✇✳❛♠✐✳❛❝✳✉❦✴❝♦✉rs❡s✴t♦♣✐❝s✴✵✶✻✹❴❤♦♠t✴ ◮ High temperature solder alloys not practical ◮ Need to decorrelate process temperature and melting point: ◮ Sintering (solid state, process below melting point) ◮ Diffusion soldering/TLPB (creation of a high melting point alloy) 17 / 45

  16. High Temperature Die Attaches – PhD A. M ASSON ◮ development of the sintering process ◮ Nano-particles paste from NBE Tech ◮ Evaluation of many parameters ◮ Sintering pressure ◮ Surface roughness ◮ Thickness of stencil ◮ Substrate finish. . . ◮ Once set, process is robust 18 / 45

  17. High Temperature Die Attaches – PhD A. M ASSON ◮ development of the sintering process ◮ Nano-particles paste from NBE Tech ◮ Evaluation of many parameters ◮ Sintering pressure 70 ◮ Surface roughness 60 Shear strenght [MPa] ◮ Thickness of stencil 50 ◮ Substrate finish. . . 40 ◮ Once set, process is robust 30 20 10 0 A’ B C D E F J N O T Series name 18 / 45

  18. High Temperature Die Attaches – PhD A. M ASSON ◮ development of the sintering process ◮ Nano-particles paste from NBE Tech ◮ Evaluation of many parameters ◮ Sintering pressure 70 ◮ Surface roughness 60 Shear strenght [MPa] ◮ Thickness of stencil 50 ◮ Substrate finish. . . 40 ◮ Once set, process is robust 30 20 10 SiC 0 A’ B C D E F J N O T Ag Series name Cu 18 / 45

  19. High Temperature Die Attaches – PhD S. H ASCOËT ◮ “Pressureless” sintering process ◮ Based on micro-particles ◮ Findings: ◮ Oxygen is necessary ◮ Bonding on copper (oxide) ◮ Standard Ni/Au finish not ideal ◮ Confirmed by several teams ◮ weak bonds at Ag/Au interface ◮ Bond strength lower ◮ Porosity higher ◮ Can be used to attach fragile components 19 / 45

  20. High Temperature Die Attaches 250 200°C 200 150 V out [V] 100 50 0 50 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] 5 200°C 4 ◮ All-sintered assembly 3 ◮ Half-Bridge structure I out [A] 2 ◮ SiC JFETs 1 ◮ Integrated gate drivers (Ampère) 0 ◮ Ceramic capacitors 1 ◮ Isolation function not integrated 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] 20 / 45

  21. High Temperature Die Attaches 250 210°C 200 150 V out [V] 100 50 0 50 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] 5 210°C 4 ◮ All-sintered assembly 3 ◮ Half-Bridge structure I out [A] 2 ◮ SiC JFETs 1 ◮ Integrated gate drivers (Ampère) 0 ◮ Ceramic capacitors 1 ◮ Isolation function not integrated 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] 20 / 45

  22. High Temperature Die Attaches 250 220°C 200 150 V out [V] 100 50 0 50 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] 5 220°C 4 ◮ All-sintered assembly 3 ◮ Half-Bridge structure I out [A] 2 ◮ SiC JFETs 1 ◮ Integrated gate drivers (Ampère) 0 ◮ Ceramic capacitors 1 ◮ Isolation function not integrated 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] 20 / 45

  23. High Temperature Die Attaches 250 230°C 200 150 V out [V] 100 50 0 50 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] 5 230°C 4 ◮ All-sintered assembly 3 ◮ Half-Bridge structure I out [A] 2 ◮ SiC JFETs 1 ◮ Integrated gate drivers (Ampère) 0 ◮ Ceramic capacitors 1 ◮ Isolation function not integrated 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] 20 / 45

  24. High Temperature Die Attaches 250 240°C 200 150 V out [V] 100 50 0 50 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] 5 240°C 4 ◮ All-sintered assembly 3 ◮ Half-Bridge structure I out [A] 2 ◮ SiC JFETs 1 ◮ Integrated gate drivers (Ampère) 0 ◮ Ceramic capacitors 1 ◮ Isolation function not integrated 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] 20 / 45

  25. High Temperature Die Attaches 250 250°C 200 150 V out [V] 100 50 0 50 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] 5 250°C 4 ◮ All-sintered assembly 3 ◮ Half-Bridge structure I out [A] 2 ◮ SiC JFETs 1 ◮ Integrated gate drivers (Ampère) 0 ◮ Ceramic capacitors 1 ◮ Isolation function not integrated 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] 20 / 45

  26. High Temperature Die Attaches 250 260°C 200 150 V out [V] 100 50 0 50 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] 5 260°C 4 ◮ All-sintered assembly 3 ◮ Half-Bridge structure I out [A] 2 ◮ SiC JFETs 1 ◮ Integrated gate drivers (Ampère) 0 ◮ Ceramic capacitors 1 ◮ Isolation function not integrated 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] 20 / 45

  27. High Temperature Die Attaches 250 270°C 200 150 V out [V] 100 50 0 50 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] 5 270°C 4 ◮ All-sintered assembly 3 ◮ Half-Bridge structure I out [A] 2 ◮ SiC JFETs 1 ◮ Integrated gate drivers (Ampère) 0 ◮ Ceramic capacitors 1 ◮ Isolation function not integrated 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] 20 / 45

  28. High Temperature Die Attaches 250 280°C 200 150 V out [V] 100 50 0 50 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] 5 280°C 4 ◮ All-sintered assembly 3 ◮ Half-Bridge structure I out [A] 2 ◮ SiC JFETs 1 ◮ Integrated gate drivers (Ampère) 0 ◮ Ceramic capacitors 1 ◮ Isolation function not integrated 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] 20 / 45

  29. High Temperature Die Attaches 250 290°C 200 150 V out [V] 100 50 0 50 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] 5 290°C 4 ◮ All-sintered assembly 3 ◮ Half-Bridge structure I out [A] 2 ◮ SiC JFETs 1 ◮ Integrated gate drivers (Ampère) 0 ◮ Ceramic capacitors 1 ◮ Isolation function not integrated 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] 20 / 45

  30. High Temperature Die Attaches 250 300°C 200 150 V out [V] 100 50 0 50 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] 5 300°C 4 ◮ All-sintered assembly 3 ◮ Half-Bridge structure I out [A] 2 ◮ SiC JFETs 1 ◮ Integrated gate drivers (Ampère) 0 ◮ Ceramic capacitors 1 ◮ Isolation function not integrated 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] 20 / 45

  31. High Temperature Die Attaches 250 310°C 200 150 V out [V] 100 50 0 50 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] 5 310°C 4 ◮ All-sintered assembly 3 ◮ Half-Bridge structure I out [A] 2 ◮ SiC JFETs 1 ◮ Integrated gate drivers (Ampère) 0 ◮ Ceramic capacitors 1 ◮ Isolation function not integrated 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] 20 / 45

  32. High Temperature Die Attaches – Silver migration, R. R IVA T = 300°C 1E-2 -1 ) 1/t (h Stop parameter 1E -3 Without parylene Parylene SCS HT 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 Electric Field (V/mm) ◮ Causes: electric field, high temperature and oxygen ◮ Large differences between similar test vehicles: ◮ Short life without encapsulation (100–1000 h) ◮ Much longer life with parylene HT protection 21 / 45

  33. High Temperature Die Attaches – Silver migration, R. R IVA T = 300°C 1E-2 -1 ) 1/t (h Stop parameter 1E -3 Without parylene Parylene SCS HT 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 Electric Field (V/mm) ◮ Causes: electric field, high temperature and oxygen ◮ Large differences between similar test vehicles: ◮ Short life without encapsulation (100–1000 h) ◮ Much longer life with parylene HT protection 21 / 45

  34. Conclusion on Packaging for High Temperature SiC devices can operate at high temperature (>300 ° C) ◮ With efficient thermal management! ◮ R Th must remain low Silver sintering for high temperature die attaches ◮ Compatible with standard die finishes ◮ Very good results ◮ High thermal/electrical performance ◮ Industry is catching on ◮ Research: long-term behaviour at elevated temperature ◮ pressureless processes are a good model 22 / 45

  35. Outline Professional Record Background Contributions Packaging for High Temperatures New Packaging Structures for Power Modules Perspectives New Packaging Structures for Power Modules Packaging for High Temperature Packaging for High Voltages Conclusion 22 / 45

  36. New Structures 23 / 45

  37. New Structures 23 / 45

  38. New Structures 23 / 45

  39. New Packaging Structures – Macro post 1 ◮ Dies soldered to two DBC substrates to form a “sandwich” module; ◮ Power module clamped between heat-exchangers; ◮ Connection to DC capacitors using a low inductance link. 24 / 45

  40. New Packaging Structures – Macro post 1 ◮ Dies soldered to two DBC substrates to form a “sandwich” module; ◮ Power module clamped between heat-exchangers; ◮ Connection to DC capacitors using a low inductance link. 24 / 45

  41. New Packaging Structures – Macro post 1 ◮ Dies soldered to two DBC substrates to form a “sandwich” module; ◮ Power module clamped between heat-exchangers; ◮ Connection to DC capacitors using a low inductance link. 24 / 45

  42. New Packaging Structures – Macro post 1 ◮ Dies soldered to two DBC substrates to form a “sandwich” module; ◮ Power module clamped between heat-exchangers; ◮ Connection to DC capacitors using a low inductance link. 24 / 45

  43. New Packaging Structures – Macro post 1 ◮ “top” heat-exchanger; ◮ power modules ◮ “bottom” heat-exchanger; ◮ driver boards; ◮ driver interconects; ◮ driver cover ◮ capacitor board; ◮ power terminals; ◮ busbar; ◮ capacitor cover. 25 / 45

  44. New Packaging Structures – Macro post 1 ◮ “top” heat-exchanger; ◮ power modules ◮ “bottom” heat-exchanger; ◮ driver boards; ◮ driver interconects; ◮ driver cover ◮ capacitor board; ◮ power terminals; ◮ busbar; ◮ capacitor cover. 25 / 45

  45. New Packaging Structures – Macro post 1 ◮ “top” heat-exchanger; ◮ power modules ◮ “bottom” heat-exchanger; ◮ driver boards; ◮ driver interconects; ◮ driver cover ◮ capacitor board; ◮ power terminals; ◮ busbar; ◮ capacitor cover. 25 / 45

  46. New Packaging Structures – Macro post 1 ◮ “top” heat-exchanger; ◮ power modules ◮ “bottom” heat-exchanger; ◮ driver boards; ◮ driver interconects; ◮ driver cover ◮ capacitor board; ◮ power terminals; ◮ busbar; ◮ capacitor cover. 25 / 45

  47. New Packaging Structures – Macro post 1 ◮ “top” heat-exchanger; ◮ power modules ◮ “bottom” heat-exchanger; ◮ driver boards; ◮ driver interconects; ◮ driver cover ◮ capacitor board; ◮ power terminals; ◮ busbar; ◮ capacitor cover. 25 / 45

  48. New Packaging Structures – Macro post 1 ◮ “top” heat-exchanger; ◮ power modules ◮ “bottom” heat-exchanger; ◮ driver boards; ◮ driver interconects; ◮ driver cover ◮ capacitor board; ◮ power terminals; ◮ busbar; ◮ capacitor cover. 25 / 45

  49. New Packaging Structures – Macro post 1 ◮ “top” heat-exchanger; ◮ power modules ◮ “bottom” heat-exchanger; ◮ driver boards; ◮ driver interconects; ◮ driver cover ◮ capacitor board; ◮ power terminals; ◮ busbar; ◮ capacitor cover. 25 / 45

  50. New Packaging Structures – Macro post 1 ◮ “top” heat-exchanger; ◮ power modules ◮ “bottom” heat-exchanger; ◮ driver boards; ◮ driver interconects; ◮ driver cover ◮ capacitor board; ◮ power terminals; ◮ busbar; ◮ capacitor cover. 25 / 45

  51. New Packaging Structures – Macro post 1 ◮ “top” heat-exchanger; ◮ power modules ◮ “bottom” heat-exchanger; ◮ driver boards; ◮ driver interconects; ◮ driver cover ◮ capacitor board; ◮ power terminals; ◮ busbar; ◮ capacitor cover. 25 / 45

  52. New Packaging Structures – Macro post 1 ◮ “top” heat-exchanger; ◮ power modules ◮ “bottom” heat-exchanger; ◮ driver boards; ◮ driver interconects; ◮ driver cover ◮ capacitor board; ◮ power terminals; ◮ busbar; ◮ capacitor cover. 25 / 45

  53. New Packaging Structures – Macro post 1 ◮ “top” heat-exchanger; ◮ power modules ◮ “bottom” heat-exchanger; ◮ driver boards; ◮ driver interconects; ◮ driver cover ◮ capacitor board; ◮ power terminals; ◮ busbar; ◮ capacitor cover. 25 / 45

  54. New Packaging Structures – Macro post 1 26 / 45

  55. New Packaging Structures – Macro post 1 700 600 500 400 V out [V] 300 200 100 0 10.1 10.2 10.3 11.7 11.8 11.9 time [ µ s] time [ µ s] ◮ Switching speed limited by switches (Si IGBTs, SiC diodes); ◮ No ringing measured at the terminals of the modules; ◮ DC link inductance estimated at 10 nH. 27 / 45

  56. New Packaging Structures – Macro post 2 (R R IVA ) V bus J H OUT J L GND ◮ Two ceramic substrates, in “sandwich” configuration ◮ Two SiC JFET dies (SiCED) ◮ assembled using silver sintering ◮ 25.4 mm × 12.7 mm (1 in × 0.5 in) 28 / 45

  57. New Packaging Structures – Macro post 2 (R R IVA ) Copper Alumina 0.16 mm 0.15 mm 0,15 mm Source Gate Source 0,3 mm ◮ Etching accuracy exceeds 0.2 mm standard design rules SiC JFET ◮ Double-step copper etching for 0.3 mm Drain die contact ➜ Custom etching technique Scale drawing for 2.4 × 2.4 mm 2 die 29 / 45

  58. New Packaging Structures – Macro post 2 (R R IVA ) 200°C 200 150 ◮ Two-step etching of copper ◮ Ti/Ag PVD using shadow mask on dies 100 V out [V] ◮ Set of aligment jigs for assembly 50 ◮ Proper drying of silver paste 0 ◮ First electrical tests on 300 Ω load 50 0.9 1.0 1.1 1.2 49.9 50.0 50.1 50.2 time [ µ s] time [ µ s] 30 / 45

  59. New Packaging Structures – Macro post 2 (R R IVA ) ◮ Good form factor achieved using the two-step copper etching process ◮ Satisfying alignment ◮ Poor quality of Al-Cu attach 31 / 45

  60. New Packaging Structures – Micro posts (B M OUAWAD ) ◮ First studies during L. M ÉNAGER PhD ◮ Copper posts growth on die (electroplating) ◮ Original die/DBC assembly technology: SnCu diffusion bonding ◮ Proposition of M. S OUEIDAN : direct copper bonding 32 / 45

  61. New Packaging Structures – Micro posts (B M OUAWAD ) Parameters: ◮ SPS press ◮ Cu/Cu bonding ◮ 5 or 20 min ◮ 200 or 300° C ◮ 16 or 77 MPa ◮ Very good bond , without any interface material ◮ All configuration but one yield to bonding ◮ Tensile strenght 106 to 261 MPa (365 MPa for bulk copper) ◮ Parameters compatible with the process of a semiconductor die ◮ Bonding mechanism still unclear ◮ Some investigations performed, much more needed 33 / 45

  62. New Packaging Structures – Micro posts (B M OUAWAD ) Parameters: ◮ SPS press ◮ Cu/Cu bonding ◮ 5 or 20 min ◮ 200 or 300° C ◮ 16 or 77 MPa ◮ Very good bond , without any interface material ◮ All configuration but one yield to bonding ◮ Tensile strenght 106 to 261 MPa (365 MPa for bulk copper) ◮ Parameters compatible with the process of a semiconductor die ◮ Bonding mechanism still unclear ◮ Some investigations performed, much more needed 33 / 45

  63. New Packaging Structures – Micro posts (B M OUAWAD ) Parameters: ◮ SPS press ◮ Cu/Cu bonding ◮ 5 or 20 min ◮ 200 or 300° C ◮ 16 or 77 MPa ◮ Very good bond , without any interface material ◮ All configuration but one yield to bonding ◮ Tensile strenght 106 to 261 MPa (365 MPa for bulk copper) ◮ Parameters compatible with the process of a semiconductor die ◮ Bonding mechanism still unclear ◮ Some investigations performed, much more needed 33 / 45

  64. New Packaging Structures – Micro posts (B M OUAWAD ) Parameters: ◮ SPS press ◮ Cu/Cu bonding ◮ 5 or 20 min ◮ 200 or 300° C ◮ 16 or 77 MPa ◮ Very good bond , without any interface material ◮ All configuration but one yield to bonding ◮ Tensile strenght 106 to 261 MPa (365 MPa for bulk copper) ◮ Parameters compatible with the process of a semiconductor die ◮ Bonding mechanism still unclear ◮ Some investigations performed, much more needed 33 / 45

  65. New Packaging Structures – Micro posts (B M OUAWAD ) ◮ “Wafer”-level process ◮ Based on copper electroplating ◮ Assembly of DBC/die/DBC “sandwiches” ◮ No damage to dies 240 25 210 180 20 150 15 120 90 10 60 5 30 0 0 0 5 10 15 20 25 34 / 45

  66. New Packaging Structures – Micro posts (B M OUAWAD ) 200 150 Forward Current [A] 100 50 To 247 Sandwich package 0 0 . 6 0 . 8 1 . 0 1 . 2 1 . 4 1 . 6 1 . 8 2 . 0 Forward Voltage [V] 16000 ◮ Higher resistance than expected 14000 12000 ◮ Due to seed layer/die topside interface 10000 Intensity ◮ Would not happen with suitable dies 0 2 8000 Ti 6000 Al 2 ◮ Simple and reproducible process AlO 2 4000 TiO CuO 2000 ◮ Tens of sample assembled, with good yield Cu 2 0 200 300 400 500 600 700 800 Sputter time [s] 35 / 45

  67. Conclusions on New Packaging Structures ◮ Several sandwich configurations: ◮ Solder ◮ Silver sintering ◮ Direct Cu/Cu bonding (Micro-posts) ◮ More suited to direct liquid cooling ◮ Solid/liquid interface ◮ Homogeneous compressing force ◮ No issue with flatness ◮ Remaining issues: ◮ Dies topside finish ◮ Mechanical relief structures ◮ Intrinsic thermo-mechanical reliability ◮ Need for further investigation 36 / 45

  68. Conclusions on New Packaging Structures ◮ Several sandwich configurations: ◮ Solder ◮ Silver sintering ◮ Direct Cu/Cu bonding (Micro-posts) ◮ More suited to direct liquid cooling ◮ Solid/liquid interface ◮ Homogeneous compressing force ◮ No issue with flatness ◮ Remaining issues: ◮ Dies topside finish ◮ Mechanical relief structures ◮ Intrinsic thermo-mechanical reliability ◮ Need for further investigation 36 / 45

  69. Conclusions on New Packaging Structures ◮ Several sandwich configurations: ◮ Solder ◮ Silver sintering ◮ Direct Cu/Cu bonding (Micro-posts) ◮ More suited to direct liquid cooling ◮ Solid/liquid interface ◮ Homogeneous compressing force ◮ No issue with flatness ◮ Remaining issues: ◮ Dies topside finish ◮ Mechanical relief structures ◮ Intrinsic thermo-mechanical reliability ◮ Need for further investigation 36 / 45

  70. Outline Professional Record Background Contributions Packaging for High Temperatures New Packaging Structures for Power Modules Perspectives New Packaging Structures for Power Modules Packaging for High Temperature Packaging for High Voltages Conclusion 36 / 45

  71. Outline Professional Record Background Contributions Packaging for High Temperatures New Packaging Structures for Power Modules Perspectives New Packaging Structures for Power Modules Packaging for High Temperature Packaging for High Voltages Conclusion 36 / 45

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