GF10x/11x Design Ove erview 2011.2.21 NVIDIA CONF FIDENTIAL - PowerPoint PPT Presentation

GF10x/11x Design Ove erview 2011.2.21 NVIDIA CONF FIDENTIAL NVIDIA CONFIDEN

Agenda Schematic Design Overview PCI-Express Memory Controller Interface Display Interface MIO(SLI) MIO(SLI) I2C GPIO Straps Power Others Others NVIDIA CONFIDENTIAL NVIDIA CONFIDEN

Schematic Design Schematic Design n Overview n Overview NVIDIA CONF FIDENTIAL NVIDIA CONFIDEN

PCI-Expre ess NVIDIA CONF FIDENTIAL NVIDIA CONFIDEN

PCI-Express Ensure PEX_RST* and PEX_RE EFCLK are connected. PEX TSTCLK OUT should be t PEX_TSTCLK_OUT should be t terminated with a 200 ohm resistor terminated with a 200 ohm resistor and made easily accessible for r probing, default can be unstuffed. PEX TEMP is used for internal _ calibration, pull-down this signal , p g with a 2.49Kohm 1% resistor. PEX_CLK_REQ* is an open-dra ain bi-directional signal, by default it should have a 10Kohm pull-u up to 3.3V, This signal is an active low signal. For default and production, PD F d f lt d d ti PD D T D TestMode to Gnd with 10K. tM d t G d ith 10K

PCI-Express Interface Power Rails PEX_IOVDD/Q – PEX_VDD PEX_PLLVDD – PEX_VDD PEX_SVDD_3V3 – 3.3V PEX PLL HVDD - 3 3V PEX_PLL_HVDD - 3.3V

PCI-Express Routing Layers: Top, Bottom Routing Layers: Top, Bottom Reference: GND Trace Impedance: 90 Ω Diff. Trace Impedance: 90 Ω Diff. Termination: On die. Place the caps within 0.3 inches Place the caps within 0.3 inches s from the connector and void the s from the connector and void the GND plane underneath. NVIDIA CONFIDENTIA

PCI-Express Plane voiding beneath AC coup Plane voiding beneath AC coup pling capacitor pling capacitor Plane voiding beneath PCI expr ress edge fingers (only for signal pads is for thickness considera p ation) PCB thickness and alignment a affecting edge finger contact NVIDIA CONFIDENTIA

M Memory Controller C t ll I t Interface f NVIDIA CONF FIDENTIAL NVIDIA CONFIDEN

Memory Controller Interfa ace To improve performance, Fermi GPUs s divide the frame buffer interface into Channels, These channels are 32bits slices made up of 4 bytes, each channel can be implemented with a single 32b b i l t d ith i l 32b bit wide DRAM component or with two bit id DRAM t ith t 16bit wide parts. Every channel can issue different comma ands Every channel can read/write to independ dent addresses. Each channel contains a fully indepen ndent memory controller. All memories within a channel share t All memories within a channel share t the same command bus and the address the same command bus and the address bus. The different channels in a GPU are co ompletely Asynchronous to each other O l Only BL8 is supported. B 8 i d Support both x32 and x16 GDDR5 and d DDR3 DRAM modes of operation.

Memory Controller Interfa ace Memory Voltage Reference Memory Voltage Reference Use GPIO10 for Vref Ctrl NVIDIA CONFIDENTIA

Memory Controller Interfa ace Memory Voltage Reference (Vre Memory Voltage Reference (Vre ef) ef) Internal Vref is applied in Fermi G GPUs so external Vref provision is not required, the Vref pin on GPU can n be left unconnected. GDDR5 memory components als so have internal Vref for DQ and DBI signals, external Vref is recomme ended. Memory Voltage Reference Switc y g ching Voltage Name Un ‐ terminated Terminated FBVREF at RAM 50% 70% NVIDIA CONFIDENTIA

Memory Controller Interfa ace FBVREF Maximum Switching T FBVREF Maximum Switching T ime ime Rail Maximum Switching Time FBVREF X=20uS NVIDIA CONFIDENTIA

Memory Controller Interfa ace GPU Driver Calibration GPU Driver Calibration Default GPU Driver Calibration for Frame Buffer Interface Memory FBVDDQ FB_CAL_PU_GND FB_CAL_PD_VDDQ FB_CAL_TERM_GND GDDR5 1.5 V 40.2 Ω 40.2 Ω 60.4 Ω NVIDIA CONFIDENTIA

Display Int terface NVIDIA CONF FIDENTIAL NVIDIA CONFIDEN

Display Interface Digital Displays Digital Displays DVI-I HDMI DisplayPort Analog Displays DAC A DAC A DAC B NVIDIA CONFIDENTIA

Display Interface Digital Display Digital Display DVI is only supported on Links A A,B,E and F, Dual-Links DVI is supported on links A/B and E/F. For I2C/DDC lines, because the IF FPx_AUX_I2Cx lines are not 5V tolerance, a Level Shifter must be used to s support I2C.DDC. For unused IFP Marco, pull-down , p n IFPxyIOVDD and IFPxy PLLVDD with a y y_ 10Kohm resistor, the other IO pin ns can be left not connected (NC). gital Display Link IFPA(LinkA) IFPB(LinkB) IFPC(L LinkC) IFPD(LinkD) IFPE(LinkE) IFPF(LinkF) √ (Dual Link with IFPB) √ (Dual Link with IFPA) √ (D ith IFPB) √ (D √ (Dual Link with IFPF) √ (Dual Link with √ (D ith IFPF) √ (D DVI x x DVI l Li k l Li k ith IFPA) l Li k l Li k ith √ √ √ √ HDMI x x √ √ √ √ Mini-HDMI x x √ √ √ Display Port x x x √ √ √ Mini-DP x x x

Display Interface DVI connection at IFPAB NVIDIA CONFIDENTIA

Display Interface HDMI at IFPx HDMI at IFPx AC Coupling Caps 499 ohm PD 499 ohm PD I2C 3V3 to 5V LevelShift NVIDIA CONFIDENTIA

Display Interface - DisplayPort NVIDIA CONFIDENTIA

Display Interface - Display yPort AUX Link in native mode NVIDIA CONFIDENTIA

Display Interface Digital Display Interface Power Digital Display Interface Power Rails Rails TMDS Power Rails Power Rails Voltage Maximum Current Draw IFPA IO: 300mA IFPA_IO: 300mA IFPx_IOVDD 3.3V±5% IFPB_IO: 200mA IFPx_PLLVDD 1.05V±5% 200mA HDMI Power Rails Power Rails Voltage Maximum Current Draw IFPx_IOVDD 1.05V±5% 285mA IFPy_PLLVDD 3.3V±5% 200mA Display Port Power Rails Power Rails Voltage Maximum Current Draw IFPx_IOVDD 1.05V±5% 300mA IFPy_PLLVDD 3.3V±5% 200mA NVIDIA CONFIDENTIA

Display Interface Analog Displays Analog Displays NVIDIA CONFIDENTIA

Display Interface Analog Display Analog Display The D12x GPUs feature two RGB DACs s that support legacy connectors. The two DACs are named DAC A and DAC B B. There is no Macrovision support in this family GPUs family GPUs. DAC VREF requires 0.1uF decoupling c capacitor. DAC Analog RGB Microvision M DAC A DAC A Supported S t d Not supported N t N N t d DAC B Supported N Not supported

Display Interface Analog Display Interface Power R Analog Display Interface Power R Rails Rails Power Rails Voltage Maximum Current Draw 3.3V ± 5% DACx_VDD 120mA

Display Interface VGA Signal Terminations Use a 37.5 Ω ± 2% trace impedance between th e GPU and the first 150 Ω resistor (R1) if the trace length is not short The trace length should not exceed 6 not short. The trace length should not exceed 6 600 mil Next use a 50 Ω ± 2% trace impedance between the 600 mil. Next, use a 50 Ω ± 2% trace impedance between the resistor R1 and the resistor R2. The trace lengt th should not exceed 6000 mil. Place the filter after the second termination res sistor, R2. The trace length should not exceed120 mil and have an impedance of 50 Ω . The trace length (75 Ω trace) between the filter and the connector should not exceed 600 mil. NVIDIA CONFIDENTIA

Display Interface Analog Display Analog Display If the DAC interface is not requ uired, it should be disabled by: Adding a pull-down to the D Adding a pull down to the D DACx VDD with a 10 k Ω resistor to DACx_VDD with a 10 k Ω resistor to GND. Unused DDC clock and da ta signals should be connected to a g 5 V pull-up. All other I/O pins (including g DACx_VREF and DACx_RSET) can be left unconnected (N NC)

MULTI-USE I/O (MIO) AND SLI NVIDIA CONFIDENTIA

MULTI-USE I/O (MIO) AND D SLI MIO(SLI) ( ) MIOA/B Calibration Resistors MIO MIOx_CAL_PD_VDDQ CAL PD VDDQ MIO MIOx_CAL_PU_GND CAL PU GND Calibration Resistor 50 ohm 1% 0402 tied to MIOx_VD DDQ 50 ohm 1% 0402 tied to GND NVIDIA CONFIDENTIA

MULTI-USE I/O (MIO) AND D SLI Interface Power Rails. Power Rails Voltage Maxim umCurrent Draw 120mA A/non ‐ SLI, VDD33 33 3.3V±5% 3.3 5% 285mA 85 A/SLI /S Unconnected Signals(NC) For unused MIOS interfaces, MIOx_ For unused MIOS interfaces MIOx _VDDQ must be powered with 3.3V for VDDQ must be powered with 3 3V for compatible designs (For GF104, mu ust connect to 3V3 even it’s no use) or pulled down to GND. For each unused MIO interface that t is powered by 3.3V, provide one 0.1uF capacitor. For MIO interfaces that h have MIOx_VDDQ that are pulled down to GND that capacitor is not needed. p MIOxCLKIN signals should have 10K Kohm pull-down resistors.

I2C NVIDIA CONFIDENTIA

I2C I2C Specification I2C Specification Parameter Specificatioin Notes A two ‐ write(SCL and SDA) I/O O BUS for miscellaneous chip to c i ll hi chip hi Overview communication Standard Mode: Up to 10 00KHz Operating Frequency p g q y Fast Mode: 400KHz Single ‐ ended Topology Bi ‐ directional 2.2K ohm pull ‐ up resistor on n I2C CLK Termination Termination and DATA and DATA Max Capacitive Load for Standard mode: 400p pF BUS Line(CL) Fast Mode: 100pF NVIDIA CONFIDENTIA