Gates - Part 1 September 11, 2008 – Typeset by Foil T EX –
Gates are built with Transistors Drain Drain Drain Gate No 3 volts Current 0 volts Current Flows Flows Source Source Source nFet nFet On nFet Off N-type field-effect transistor = nFet – Typeset by Foil T EX – 1
Gates are built with Transistors Drain Drain Drain Gate No 0 volts Current 3 volts Current Flows Flows Source Source Source pFet pFet On pFet Off P-type field-effect transistor = pFet – Typeset by Foil T EX – 2
Complement Also known as invert or not. X X’ X F 0 1 This is a schematic symbol. 1 0 It is a graphical representation of a circuit which implements the operations. – Typeset by Foil T EX – 3
FET-Based Inverter V cc = 3V V cc = 3V V cc = 3V OFF ON Vin Vout 3V 0V 0V 3V ON OFF GND = 0V GND = 0V GND = 0V – Typeset by Foil T EX – 4
AND and OR Gates And Gate A B Y = A • B 0 0 0 A Y=A * B 0 1 0 B 1 0 0 1 1 1 Or Gate A B Y = A + B 0 0 0 Y = A + B A 0 1 1 B 1 0 1 1 1 1 – Typeset by Foil T EX – 5
Boolean Expressions and Gates Each boolean expression has a corresponding realization with logic gates. F = A’ + BC A F B C – Typeset by Foil T EX – 6
NAND Gates NAND AND A B F=(A • B)’ 0 0 1 A Y=A * B 0 1 1 B Y is true iff A AND B are true 1 0 1 1 1 0 NAND A Y = not(A * B) A Y=not(A*B) B B A Y is false iff A AND B are true Y=not(A*B) B – Typeset by Foil T EX – 7
FET-Based NAND Gate Vcc Vcc Vcc 0 1 1 OFF OFF A B 1 OFF ON 0 F 1 A ON 1 1 ON B 0 OFF 1 ON GND GND GND – Typeset by Foil T EX – 8
NOR Gates NOR OR A B F=(A + B)’ Y = A + B A 0 0 1 B 0 1 0 Y is true if A OR B are true 1 0 0 1 1 0 NOR Y = not(A + B) A Y = not(A or B) A B B Y = not(A or B) Y is false if A OR B are true A B – Typeset by Foil T EX – 9
FET-based NOR Gate Vcc A B F A 0v 0v ? 0v 5v ? B 5v 0v ? F 5v 5v ? A B Can you complete the truth table? GND – Typeset by Foil T EX – 10
FET-Based Gates • P-type FETs must be on top of gate • N-type FETs must be on bottom of gate – Due to electrical characteristics of the two FET types • Output is driven to either ’1’ or ’0’ – never both – never neither – Typeset by Foil T EX – 11
Exclusive-OR (XOR) Output is true if and only if inputs are different. A B Q = A ⊕ B A Q 0 0 0 B 0 1 1 1 0 1 Q = A ⊕ B = A’B + AB’ 1 1 0 Another definition: Q is true if A � = B. – Typeset by Foil T EX – 12
Exclusive-OR Theorems X ⊕ 0 = X X ⊕ 1 = X’ X ⊕ X = 0 X ⊕ X’ = 1 X ⊕ Y = Y ⊕ X Commutative law (X ⊕ Y) ⊕ Z = X ⊕ (Y ⊕ Z) = X ⊕ Y ⊕ Z Associative law (X ⊕ Y)’ = X ⊕ Y’ = X’ ⊕ Y The first four are important, the others are used less frequently. – Typeset by Foil T EX – 13
Equivalence Operation ≡ denotes equivalence (also written as X==Y) Output is true if and only if inputs are equal X Y X ≡ Y A Q 0 0 1 B 0 1 0 1 0 0 Q = (X ≡ Y) = X’Y’ + XY 1 1 1 – Typeset by Foil T EX – 14
XOR and EQUIV are complements X Y X ⊕ Y X ≡ Y 0 0 0 1 0 1 1 0 1 0 1 0 1 1 0 1 A Q Alternate symbol B Bubble means NOT. This gate is often called exclusive NOR or XNOR. – Typeset by Foil T EX – 15
Multi-Input Gates Vcc Vcc A B A B C F F A A B B C GND GND Which one will be slower/faster? Electricity moves at the speed of light. – Typeset by Foil T EX – 16
Alternative Gate Symbols The symbolic meaning of the circuit should be clear from what you draw. Alternative symbols can reduce some gate requirements. – Typeset by Foil T EX – 17
Alternative Gate Symbols A Q B Q is true if A is false OR B is false. A Q B Q is true if and only if A is false and B is false. – Typeset by Foil T EX – 18
Alternative Gate Symbols X Y Q 0 0 1 A 0 1 1 Q B A 1 0 1 Q B Q is true if A is false OR B is false. 1 1 0 A Q X Y Q B A 0 0 1 Q Q is true if and only if A is false B 0 1 0 and B is false. 1 0 0 1 1 0 – Typeset by Foil T EX – 19
Alternative Gate Symbols Turn on sprinklers if it is not a holiday and it is not a weekend. A A Q Q B or? B տ The problem statement uses AND, so use the AND symbol. – Typeset by Foil T EX – 20
Alternative Gate Symbols Turn off sprinklers if it is a holiday or it is a weekend. A A Q Q B or? B ր The problem statement uses OR, so use the OR symbol. – Typeset by Foil T EX – 21
Another Example Design a circuit to determine whether the bits of a 4-bit wire are all zero. – Typeset by Foil T EX – 22
Another Example Design a circuit to determine whether the bits of a 4-bit wire are all zero. This is the appropriate symbol to use. – Typeset by Foil T EX – 23
Mixed Symbols A Q B Q is true iff A is false AND B is true • Such a gate doesn’t likely exist • Build from AND gate and inverter • Simplifies schematics and enhanced readability – Typeset by Foil T EX – 24
Single Gate Conversion Rules • Change symbol – AND to OR – OR to AND • Invert all inputs and outputs • No change in behavior – merely a symbol change A A Q Q B B Q is true iff A is false AND B is true Q is false if A true OR B is false. – Typeset by Foil T EX – 25
Alternative Gate Symbols - Summary • Use the symbol that matches the problem statement – Clarity – Documentation – Maintenance • If function is correct but symbol is wrong, then your schematic is wrong. – Typeset by Foil T EX – 26
Positive vs Negative Logic v1 v2 v3 vout 0v 0v 0v 0v v1 Logic 0v 0v 5v 0v v2 vout 0v 5v 0v 0v Gate v3 0v 5v 5v 0v 5v 0v 0v 0v 5v 0v 5v 0v 5v 5v 0v 0v 5v 5v 5v 5v – Typeset by Foil T EX – 27
Positive Logic Let: O volts → 0 5 volts → 1 v1 v2 v3 vout v1 v2 v3 vout 0v 0v 0v 0v 0 0 0 0 0v 0v 5v 0v 0 0 1 0 0v 5v 0v 0v 0 1 0 0 0v 5v 5v 0v 0 1 1 0 5v 0v 0v 0v 1 0 0 0 5v 0v 5v 0v 1 0 1 0 5v 5v 0v 0v 1 1 0 0 5v 5v 5v 5v 1 1 1 1 The circuit is a logical AND gate. – Typeset by Foil T EX – 28
Negative Logic Let: O volts → 1 5 volts → 0 v1 v2 v3 vout v1 v2 v3 vout 0v 0v 0v 0v 1 1 1 1 0v 0v 5v 0v 1 1 0 1 0v 5v 0v 0v 1 0 1 1 0v 5v 5v 0v 1 0 0 1 5v 0v 0v 0v 0 1 1 1 5v 0v 5v 0v 0 1 0 1 5v 5v 0v 0v 0 0 1 1 5v 5v 5v 5v 0 0 0 0 The same is a circuit logical OR gate. – Typeset by Foil T EX – 29
Positive/Negative Logic The most common mapping is: +V ⇐ ⇒ 1 0V ⇐ ⇒ 0 Different systems have used different mappings in the past. – Typeset by Foil T EX – 30
Multi-Level Logic – Typeset by Foil T EX – 31
Levels of a network Maximum number of gates between an input and the output 5 Level In general, the more levels, the slower the circuit. 3 Level – Typeset by Foil T EX – 32
Number of Levels • Number of levels can be increased by factoring. G = AB + ACDE + ACF = A(B+CDE+CF) • Number of levels can be descreased by multiplying out.. G = A(B+CDE+CF) = AB + ACDE + ACF – Typeset by Foil T EX – 33
Example Levels = 2 #Gates = 4 Delay = t and 4 + t or 3 G = AB + ACDE + ACF #Inputs = 12 #transistors = 24 Largest gate = 4 inputs A B A Area calculations: C G D • each input to a gate costs 2 transistors E A • area ∝ # of transistors C Delay calculations: F • find the slowest past from inputs to outputs t delay = t and 4 + t or 3 • the 4-input AND is likely slower than the other AND gates. – Typeset by Foil T EX – 34
Change the number of levels by factoring G = ACDE + ACF + AB = A(CDE + CF + B) factor → C Levels = 3 D #Gates = 4 E Delay = t and 3 + t or 3 + C G t and 2 F A #Inputs = 10 B #transistors = 20 Largest gate = 3 inputs This is a 3-level circuit. – Typeset by Foil T EX – 35
Factor Again G = A(CDE + CF + B) = A(B+C(F+DE)) factor → Levels = 5 #Gates = 5 B D C G Delay = 3 × t and 2 + 2 × t or 2 E A F #Inputs = 10 #transistors = 20 This is a 5 -level circuit. Largest gate = 2 inputs – Typeset by Foil T EX – 36
Changing the number of levels Three alternative solutions for the same function... 2-level 3-level 4-level Logic Levels 2 3 5 Delay 3 × t and 2 + 2 × t or 2 t and 4 + t or 3 t and 3 + t or 3 + t and 2 Gate Count 4 4 5 Gate Inputs 12 10 10 Transistors 24 20 20 Largest gate 4 3 2 Each has different area/speed characteristics. – Typeset by Foil T EX – 37
Two-Level vs. Multi-Level • In general: – two-level is fastest – multi-level can be smaller • Exploring by hand to find just the right solution can be difficult • We will focus on two-level – easy to get from truth table – minimization techniques in later chapters focus on it – Typeset by Foil T EX – 38
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