��������������������� � ����������� � ����������� Foundations of Combinational Circuits
Checking a Circuit Mapping the circuit into a directed graph G(V,E). Each gate is a vertex � Each output terminal defines a net � Each net is transformed into edges from the output terminal to each of � the input terminals. Single net IN AND OR XOR OUT NOT IN
Graph Representation by List of Neighbors 1 3 5 6 8 2 3 7 5 6 4 5 2 8 6 7 8
Graph Representation by Matrix 1 2 3 4 5 1 v 2 3 v 4 5 v
Checking a Circuit • If a terminal has two incoming edges, then it is fed by two nets, which is illegal. In that case we stop and return FALSE. Two inputs to IN one terminal ! AND OR XOR OUT NOT IN
Testing for Circles • In order to test for circles we need to run a Depth-First-Search (DFS) algorithm on the graph, and check for any backwards edges during the execution of the algorithm.
DFS Example Stack 1 2 5 3 4
DFS Stack 1 2 5 3 1 4 = Currently in the stack
DFS Stack 1 2 5 3 2 1 4
DFS Stack 1 2 5 3 3 2 1 4
DFS Stack 1 2 5 4 3 3 2 Backwards Edge 1 This graph has a cycle! 4
Elements of the Proof • The algorithm terminates regardless of the structure of the input graph. • If there is a cycle in the graph, the algorithm will find it (return FALSE). • If there is no cycle in the graph, the algorithm will return TRUE.
The Algorithm Terminates • The algorithm passes through every vertex only once, therefore it will always terminate after visiting all of the vertices regardless of the edges.
The Proof • Assume there is a cycle in the graph. At some point a first vertex that belongs to the cycle will be reached. All other vertices of the cycle have not been reached yet. • Before that first vertex is popped out of the stack, the DFS procedure guarantees that an edge closing the cycle and entering that vertex will be tested. • It is a backwards edge.
The Proof • Immediate, but nevertheless: • Assume there are no cycles in the graph. • Backwards edges cannot exist since they require a path from a successor to a predecessor, which means there is a cycle.
Topological Sort • Works only on Directed Acyclic Graphs (DAG). • The Algorithm: – Form a set of all independent vertices - those that have no incoming edges. There must be at least one! – While the set is empty: Pick any vertex v from the set. If any of its successors have no other predecessors – add them to the set of independent vertices. Erase all of the edges originating at v .
Topological Sort Example IN AND OR XOR OUT NOT IN = Independent Vertex
Topological Sort Example IN AND OR XOR OUT NOT IN The Topological Sort: IN
Topological Sort Example IN AND OR XOR OUT NOT IN The Topological Sort: IN IN
Topological Sort Example IN AND OR XOR OUT NOT IN The Topological Sort: IN IN OR
Topological Sort Example IN AND OR XOR OUT NOT IN The Topological Sort: IN IN OR AND
Topological Sort Example IN AND OR XOR OUT NOT IN The Topological Sort: IN IN OR AND NOT
Topological Sort Example IN AND OR XOR OUT NOT IN The Topological Sort: IN IN OR AND NOT XOR
Topological Sort Example IN AND OR XOR OUT NOT IN The Topological Sort: IN IN OR AND NOT XOR OUT
Testing for Cycles during Topological Sort IN AND OR XOR OUT NOT IN There are nodes left, but none are independent Cycle!
Propagation Delay T Max { t } = pd pd all paths There is always at least one “critical path”. What is the propagation delay of a circuit that is not acyclic?
Finding the Propagation Delay t ( v ) Max { t ( v ' ) t ( v ' )} = + pd inputs v ' predecesso r ( v ) inputs ∈ ready ready Now, using the fact that it is an acyclic graph, we go through the topological order from start to beginning, each time updating the “inputs ready” time of the successors. The total propagation delay is the maximal “inputs ready” time (assuming that we used output nodes).
Finding the Maximum Delay 0 0 OR AND NOT XOR OUT
A circuit with 2 n/2 paths 2 options 2 options n/2 stages with 2 options each, resulting in 2 n/2 paths. How are we computing the delay of an exponential number of circuits in linear time? Let’s go to the previous slide.
A circuit with 2 n paths • …cannot be built! • Why? A combinational circuit is a DAG, therefore we cannot reorder the gates to create different paths. Our only option is to include or exclude gates to create different paths. • But, having n gates, we only have 2 n such paths. Each gate can be included or excluded, therefore 2 n . • We cannot build this circuit since we will require an unbounded in-degree of the gates.
XOR is Associative – part I Definition XOR ( a , b ) ( ab ' a ' b ) = + XOR ( XOR ( a , b ), c ) ( ab ' a ' b ) c ' ( ab ' a ' b ) c = + + + De Morgan 1 st Expanded ( ab ' a ' b ) c ' ( ab ' a ' b ) c = + + ⋅ definition De Morgan ( ab ' a ' b ) c ' ( a ' b )( a b ' ) c = + + + + ( ab ' a ' b ) c ' ( a ' a ba a ' b ' bb ' ) c Distributive = + + + + + ( ab ' a ' b ) c ' ( ab a ' b ' ) c = + + + Complement ab ' c ' a ' bc ' abc a ' b ' c = + + + Distributive
XOR is Associative – part 2 Definition XOR ( a , b ) ( ab ' a ' b ) = + XOR ( a , XOR ( b , c )) a ( bc ' b ' c ) a ' ( bc ' b ' c ) = + + + De Morgan 2 nd Expanded a ( bc ' b ' c ) a ' ( bc ' b ' c ) = ⋅ + + definition De Morgan a ( b ' c )( b c ' ) a ' ( bc ' b ' c ) = + + + + a ( b ' b cb b ' c ' cc ' ) a ' ( bc ' b ' c ) Distributive = + + + + + a cb b c a bc b c ( ' ' ) ' ( ' ' ) = + + + Complement acb ab ' c ' a ' bc ' a ' b ' c = + + + Distributive
THE END
Recommend
More recommend
