T-Micro 3D-IC technology trends and current development status for the stacked pixel detectors Makoto Motoyoshi Tohoku-MicroTec July 6, 2017 @ Fermi Lab. T-Micro / Motoyoshi 1
T-Micro Outline 1 ． Introduction - Advantages of 3D-LSI - Road Map/Potential Application 2 ． Technology Approach - TSV process - Bond/Stack approaches - Examples of 3D integration 3. Pixel detectors - Background - Au cone bump using NpD method - Cylinder Bump for fragile semiconductor material ４ . 3D Cost reduction approach 5 ． Summary July 6, 2017 @ Fermi Lab. T-Micro / Motoyoshi 2
T-Micro LSI Technology 3D-IC Technology - Predictable - unpredictable - Precisive but inflexible Application driven technology - Need flexibility System technology Many integration methods July 6, 2017 @ Fermi Lab. T-Micro / Motoyoshi 3
T-Micro 3DIC Supply chain Base devices 4 inch Si wafer 6 inch Si wafer 8 inch Si wafer 12 inch Si wafer Shuttle service (LSI Chip) 3D Compound Semiconductor (Chip/Wafer) integration July 6, 2017 @ Fermi Lab. T-Micro / Motoyoshi 4
T-Micro Unique Points of 3D-LSI Conventional SoC 3D-SoC Compound semiconductor Length of TSV: 1-50 m m Sync. clock Repartitioning Die -Short global interconnect Long Global interconnect small RC delay, small C P large RC delay, large C P -High band width -Small form factor 1. Increase of electrical performances 2. Increase of circuit density 3. New Architecture (Hyper-parallel processing, Multifunction, etc) 4. Heterogeneous integration 5. Better yield TSV ： Through Silicon Via July 6, 2017 @ Fermi Lab. T-Micro / Motoyoshi 5
T-Micro Chip & System Integration Trends for better PPA & System Performance Source: Cliff Hou (TSMC), ISSCC 2017 (Plenary) July 6, 2017 @ Fermi Lab. T-Micro / Motoyoshi 6
T-Micro Key technologies of 3D-IC Integration Wafer thinning 775 μ m 50~10 μ m Over coat metal Top tier SiO2 N + N + SiO2 SiO2 P + P + Nch-MOSFET Pch-MOSFET metal satisfy LSI reliability test Chip Alignment N + SiO2 N + SiO2 P + P + Middle tier Pch-MOSFET PWell PWell metal metal P + SiO2 N + N + SiO2 P + Bottom tier Nch-MOSFET NWell NWell Si Substrate Micro bump TSV (Through Silicon Via) July 6, 2017 @ Fermi Lab. T-Micro / Motoyoshi 7
T-Micro TSV process classification Stacking Allowable max. process Thinning 450~350ºC > temperature 1000ºC > 600ºC > FEOL BEOL Handle Well glass MOS Interlayer Isolation MOS process After BEOL Before MOS 1st Interlayer After MOS Handle Handle Wafer Wafer After Front Via SOI Back Via TSV step Handle Wafer Via First Via Middle Via Last July 6, 2017 @ Fermi Lab. T-Micro / Motoyoshi 8
T-Micro Wafer Bonding Methods -1 Oxide Metal Microbump Organic film （ Adhesive ） Multi-level Multi-level Multi-level metallization metallization metallization Si Si Si Metal (Cu) Fusion Bonding Adhesive Bonding Oxide Fusion Bonding Metal (Cu/SnAg) Eutetic Bonding July 6, 2017 @ Fermi Lab. T-Micro / Motoyoshi 9
T-Micro Wafer Bonding Methods -2 Organic Oxide Microbump Microbump film Multi-level Multi-level metallization metallization Si Si Adhesive/ Metal Bonding Oxide/ Metal Bonding (Hybrid bonding) July 6, 2017 @ Fermi Lab. T-Micro / Motoyoshi 10
T-Micro Various types of 3D-IC Integration Via last Via middle Via first Heterogeneous Process after BEOL before Metal Integration cost before MOS after Stack before Stack interconnect Stack Approach W, Cu, etc W, Cu, etc Poly-Si W, Cu IMEC Ziptronix 3D DRAM T-Micro(Tohoku.U) T-Micro TSMC IMEC 3D Flash Toshiba Micron Image Sensor Bulk IBM Samsung MEMS Samsung Samsung ・・・・・・・・・・・ Dalsa Hynix WoW IMEC Low Impossible Tezzaron Sony Ziptronix Toshiba IBM MIT （ Lincoln Lab. ） T-Micro SOI RPI etc. Fraunhofer IZM -Heterogeneous CEA-LETI CoW Ziptronix Integration Low~ T-Micro MEMS IMEC Middle possible etc. -Pixel detector T-Micro(Tohoku U.) 3D DRAM Micron T-Micro 3D Flash T-Micro T-Micro Samsung MEMS CoC possible Hynix Intel, Infineon, IMEC, High etc. etc. Toshiba Samsung, Toshiba July 6, 2017 @ Fermi Lab. T-Micro / Motoyoshi 11
T-Micro Yield loss by particles dusts or particles S/D S/D S/D S/D S/D S/D No failure failure No failure or reliability problem Oxide CVD CMP S/D S/D S/D S/D S/D S/D Via patterning Form metal interconnect July 6, 2017 @ Fermi Lab. T-Micro / Motoyoshi 12
T-Micro Yield loss by particles dusts or particles S/D S/D S/D S/D S/D S/D No failure failure No failure or reliability problem Oxide CVD CMP S/D S/D S/D S/D S/D S/D Via patterning Form metal interconnect We can only detect this failure from electrical testing. July 6, 2017 @ Fermi Lab. T-Micro / Motoyoshi 13
T-Micro Yield loss by particles dusts or particles S/D S/D S/D S/D S/D S/D No failure failure No failure or reliability problem Oxide CVD CMP S/D S/D S/D S/D S/D S/D Via patterning Form metal interconnect In case of bonding wafer/chip on wafer /chip surface with dust, Upper Chip Lower Chip If the bonding method which needs microscopic smoothness and cleanliness, bonding yield will be affected by defect density of dusts and particles. So we have chosen the bump bonding with adhesive injection. July 6, 2017 @ Fermi Lab. T-Micro / Motoyoshi 14
T-Micro Issue of wafer to wafer bonding (1) Shift of wafer size after wafer process Ｄ１’ Ｄ１ LSI process#1 Ｄ１’’ LSI process# ２ D1≠D1’ ≠D1’’ (2) Alignment error of wafer process Actual Ideal July 6, 2017 @ Fermi Lab. T-Micro / Motoyoshi 15
T-Micro HBM (High Band Width Memory) Commercialized 3D DRAM Source: Kyomin Sohn (Samsung), ISSCC2016 July 6, 2017 @ Fermi Lab. T-Micro / Motoyoshi 16
T-Micro Cross-sectional View and Chip Photo of HBM Source: Kyomin Sohn (Samsung), ISSCC2016 July 6, 2017 @ Fermi Lab. T-Micro / Motoyoshi 17
T-Micro Source: Kyomin Sohn (Samsung), ISSCC2016 July 6, 2017 @ Fermi Lab. T-Micro / Motoyoshi 18
T-Micro SK Hinix/ 3D DRAM (High Bandwidth Memory: HBM) July 6, 2017 @ Fermi Lab. T-Micro / Motoyoshi 19
T-Micro Sony / 3D-Stacked Image Sensor Sony’s first CIS module(IMX260) product with Cu-Cu Hybrid bonding Cu-Cu Via Top part BI-CIS 3um wide 14um pitch Middle part DRAM Cu-Cu Via 3um wide 6um pitch Bottom part Logic Source: T. Haruta (Sony) ISSCC2017 Source: Chipworks, April, 2016 July 6, 2017 @ Fermi Lab. T-Micro / Motoyoshi 20
T-Micro ITRS Road Map of TSV TSV Low-power & high- bandwidth 3D Memory &Logic Memory Density: >10TB TSV length: <10um TSV diameter: 0.5um TSV is a leading-edge technology for new generation memory. TSV scaling and increase I/O density are required for future 3D-ICs July 6, 2017 @ Fermi Lab. T-Micro / Motoyoshi 21
T-Micro High Density Memory Systens using Si Interposer July 6, 2017 @ Fermi Lab. T-Micro / Motoyoshi 22
T-Micro AMD reveals HBM-powered Radeon Fury graphics cards, new R300-series GPUs HBM (1GB, 1GbX4 Tier) Si Interposer <4900m m2 9900mm 2 Memory Interface ; Fury graphics card : $649, June, 2015 4096bit Memory Bandwidth ; 512GB/s July 6, 2017 @ Fermi Lab. T-Micro / Motoyoshi 23
T-Micro July 6, 2017 @ Fermi Lab. T-Micro / Motoyoshi 24
T-Micro July 6, 2017 @ Fermi Lab. T-Micro / Motoyoshi 25
T-Micro Monolithic 3D-IC with vertical TFT Toshiba : Flash Memory IEDM2007 July 6, 2017 @ Fermi Lab. T-Micro / Motoyoshi 26
T-Micro NAND Flash is required higher bit density Source: R. Yamashita (Western Digital/Toshiba) ISSCC 2017 July 6, 2017 @ Fermi Lab. T-Micro / Motoyoshi 27
T-Micro Highly Integrated Heterogeneous 3D Integrated System MEMS chip 3D Super Chip Sensor chip CMOS RF-IC MMIC Power IC New chip stacking Control IC technologies are Logic LSI Flash memory required DRAM SRAM Microprocessor Different Different materials devices 1.3 mm Different Metal microbump 38-layer chip stack chip size Through-Si via (TSV) July 6, 2017 @ Fermi Lab. T-Micro / Motoyoshi 28
T-Micro Fine Pitch TSV By Plating July 4th, 2017 @iWoRiD2017 T-Micro / Motoyoshi 29
T-Micro July 4th, 2017 @iWoRiD2017 T-Micro / Motoyoshi 30
T-Micro Fine Pitch TSV By Plating July 4th, 2017 @iWoRiD2017 T-Micro / Motoyoshi 31
T-Micro July 4th, 2017 @iWoRiD2017 T-Micro / Motoyoshi 32
T-Micro Contents 1. Background -Target device -Previous work 2 ． Au cone bump using NpD method 3. Cylinder Bump for fragile semiconductor material 4. ３ D Cost reduction approach 5. Summary NpD: Nano-particle deposition July 6, 2017 @ Fermi Lab. T-Micro / Motoyoshi 33
T-Micro Target device 3D Stacked Pixel Detector Si detector Micro-bump Junction Si detector Pre-amplifire Discriminator ADC Memory, Counter ROIC 3D heterogeneous stacked X-ray / IR pixel sensor Compound semiconductor X-ray --CdTe IR – HgCdTe, etc RO IC July 6, 2017 @ Fermi Lab. T-Micro / Motoyoshi 34
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