First measurements on the new FPGA-based DIRICH MAPMT readout First measurements on the new V. Patel FPGA-based DIRICH MAPMT readout Overview First test results in HADES test Vivek Patel box BergischeUniversitatWuppertal DPG Spring Meeting M¨ unster,March 2017
Overview First measurements on the new FPGA-based DIRICH HADES RICH in operation since 2000. MAPMT readout Original design was using CsI reflective photocathode + V. Patel MWPC readout for photon detection,C4F10 gas radiator, Overview hadron blind First test HADES RICH is under upgrade with newly acquired results in HADES test H12700 MAPMTs from Hamamatsu. box First beam for HADES with new photodetector is forseen to be in second half of 2018(fingers crossed..!!) Test of MAPMTs and readout electronics are currently done at Wuppertal and GSI(HADES cave).
HADES-RICH upgrade First measurements on the new FPGA-based DIRICH MAPMT readout V. Patel Overview First test results in HADES test box
Readout Electronics for RICH MAPMTs First measurements on the new Prototype of all readout modules are in test now ..!! FPGA-based DIRICH MAPMT readout V. Patel Overview First test results in HADES test box
Experimental setup in HADES cave with HADES test box First measurements Analog part of DiRICH has on the new FPGA-based been tested in HADES DIRICH MAPMT testbox. readout Single module with two V. Patel active probes connected to Overview two channels at output of First test preamp. results in HADES test The signals from preamp box thus can be visualized using an oscilloscope(4GHz-R&S oscilloscope). Storage of many individual traces for offline analysis. Simulate FPGA TDC offline with scope data.
A typical MAPMT signal on scope First measurements on the new FPGA-based DIRICH Persistancy plot of typical PMT MAPMT readout signal V. Patel After preamplification Overview Directly before First test results in discrimination+TDC HADES test box inside FPGA Picosecond pulse laser inside test setup to generate single photons
Time over threshold studies First measurements on the new FPGA-based DIRICH MAPMT readout V. Patel Overview First test results in HADES test box ToT is an effective tool to filter our data. Operating at reasonable threshold( > noise but low enough so that we conserve maximum pulse information) this can easily differentiate between signal and crosstalk. ToT of wiggle(1-2ns) is less than that of main signal(4-5ns).
Time over threshold studies ToT(Pulse width)(blue:no ToT cut red:ToT > 2ns) First measurements on the new FPGA-based DIRICH 600 Threshold 30mV Threshold 60mV MAPMT 2500 readout 500 2000 V. Patel 400 1500 300 Overview 1000 200 First test 500 100 results in × − 9 × − 9 HADES test 10 10 0 0 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 box Pulse width(s) Pulse width(s) 600 500 Threshold 90mV Threshold 150mV 500 400 400 300 300 200 200 100 100 − − × 9 × 9 10 10 0 0 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 Pulse width(s) Pulse width(s)
Time diff: Laser trigger ↔ Channel First measurements on the new FPGA-based DIRICH At low threshold we get two MAPMT readout Threshold 30mV 450 distinct peaks in leading edge V. Patel 400 timing one is main signal and 350 Overview other is wiggle. 300 First test results in Leading edge delayed by 3-4ns 250 HADES test box for wiggle due to inverse polarity 200 150 of the signal. 100 Wiggle signals can be supressed 50 completely just by applying ToT − × 9 10 0 − − − − − 10 8 6 4 2 0 2 4 6 8 10 cut > 2ns. Trig-Channel timing(s)
Time diff: Channel1 ↔ Channel2 First measurements on the new FPGA-based On analysing data with trigger on DIRICH MAPMT one of the channel we found that it readout Threshold 30mV showed three peak structure. 500 V. Patel The central peak here corresponds Overview 400 to signal(or wiggle) events in both First test the channels under observation. results in 300 HADES test box The side peaks(+/-4ns ) correspond 200 to signal in one and wiggle in other channel. 100 By applying ToT > 2ns in both the − × 9 10 channels(red curve) we can suppress 0 − − − − − 10 8 6 4 2 0 2 4 6 8 10 Channel-Channel timing(s) the side peaks.
Expected Timing precision based on scope data First measurements Time-diff: Laser ↔ Channel(blue:no Tot cut red:ToT > 2ns) on the new FPGA-based DIRICH 500 Entries Entries 14544 14544 500 Entries Entries 14544 14544 MAPMT Threshold 35mV − − Threshold 35mV − − Mean Mean 2.204e 2.204e 09 09 Mean Mean 4.174e 4.174e 10 10 − − − − Std Dev Std Dev 2.051e 2.051e 09 09 Std Dev Std Dev 4.59e 4.59e 10 10 readout 400 400 RMS : 450ps V. Patel 300 300 Gauss fit : 350ps 200 200 Overview PMT-TTS: 300 100 100 First test − − results in × 9 × 9 10 10 0 0 − − − − − − − − 10 8 6 4 2 0 2 4 6 8 10 1.5 1 0.5 0 0.5 1 1.5 2 2.5 HADES test Trig-Channel timing(s) Trig-Channel timing(s) box Time-diff: Ch1 ↔ Ch2(blue:no ToT cut red:ToT > 2ns) 140 Entries Entries 5805 5805 Entries Entries 5805 5805 Threshold 35mV − − Threshold 35mV − − − − 350 Mean Mean 7.733e 7.733e 10 10 Mean Mean 7.234e 7.234e 11 11 − − − − RMS RMS 3.399e 3.399e 09 09 RMS RMS 5.662e 5.662e 10 10 120 300 RMS : 560ps 100 250 80 Gauss fit : 450ps 200 60 150 PMT-TTS: 430 40 100 50 20 − − × 9 × 9 10 10 0 0 − − − − − − − − 10 8 6 4 2 0 2 4 6 8 10 1.5 1 0.5 0 0.5 1 1.5 Channel-Channel timing(s) Channel-Channel timing(s)
A step forward to real FPGA-TDC First measurements on the new FPGA-based DIRICH MAPMT readout V. Patel Overview So far all the analysis shown above were simlated TDC based First test on Scope Data.From last few weeks full TDC using FPGA was results in HADES test available. In following slide are the results of the same. box
Timing Measurement using FPGA-TDC First measurements on the new FPGA-based DIRICH MAPMT readout V. Patel Overview First test results in HADES test box RMS : 750ps Gauss fit : 350ps
Summary First measurements on the new First tests of readout electronics are showing promising results. FPGA-based DIRICH Time resolution obatained using scope and that with FPGA MAPMT readout based TDC are well in agreement with each other and also with V. Patel expectations proving that the DiRICH concept will work. Overview At this point 4 channels of FPGA has been programmed for First test TDC. In coming days full 32 channel TDC is expected to be results in obatained for complete system tests. HADES test box The main goal now is to check the performance of the MAPMT+DiRICH readout at COSY in real beam conditions. A small protoype box has been made for beam test at COSY with 6 MAPMT and complete set of readout electornics installed in it. Currently it is under tests at Wuppertal.
First measurements on the new FPGA-based DIRICH MAPMT readout V. Patel Overview Thank you First test results in HADES test box
Laser trigger - channels Leading edge timing(blue:no Tot cut red:ToT > 2ns) First measurements on the new FPGA-based DIRICH Threshold 30mV 350 Threshold 60mV 450 MAPMT readout 400 300 350 250 V. Patel 300 200 250 Overview 200 150 150 100 First test 100 results in 50 50 × − 9 × − 9 HADES test 10 10 0 0 − − − − − − − − − − 10 8 6 4 2 0 2 4 6 8 10 10 8 6 4 2 0 2 4 6 8 10 box Trig-Channel timing(s) Trig-Channel timing(s) 200 Threshold 90mV Threshold 150mV 180 300 160 250 140 120 200 100 150 80 100 60 40 50 20 − − × 9 × 9 10 10 0 0 − − − − − − − − − − 10 8 6 4 2 0 2 4 6 8 10 10 8 6 4 2 0 2 4 6 8 10 Trig-Channel timing(s) Trig-Channel timing(s)
Channel-Channel(self trigger) Leading edge timing(blue:no Tot cut red:ToT > 2ns) First measurements on the new FPGA-based DIRICH 120 Threshold 30mV Threshold 60mV MAPMT 500 readout 100 400 V. Patel 80 300 60 Overview 200 40 First test 100 20 results in × − 9 × − 9 HADES test 10 10 0 0 − − − − − − − − − − 10 8 6 4 2 0 2 4 6 8 10 10 8 6 4 2 0 2 4 6 8 10 box Channel-Channel timing(s) Channel-Channel timing(s) 70 Threshold 90mV Threshold 150mV 100 60 80 50 40 60 30 40 20 20 10 − − × 9 × 9 10 10 0 0 − − − − − − − − − − 10 8 6 4 2 0 2 4 6 8 10 10 8 6 4 2 0 2 4 6 8 10 Channel-Channel timing(s) Channel-Channel timing(s)
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