Fast Acquisition Techniques for Very long PN Codes for On-board - PowerPoint PPT Presentation

Fast Acquisition Techniques for Very long PN Codes for On-board Secure TT&C Transponders G. Fittipaldi 1) , L. Simone 1) , I. Aguilar Sancez 2) 1) Thales Alenia Space (TAS-I), 2 ) European Space Agency (ESA)

ToC  Introduction  ON-Board PN Code Synchronizer Architecture Description  Frequency Domain Correlation Technique  Very Large Doppler Compensation Technique  Anti-jamming Signal Processing  On-Board Codes Synchronization Processing  Simulation Results:  Detection Probability and Code Acquisition Time for GSO-MEO and LEO Satellite Applications  Conclusions

Introduction  Scenario: Today Satellite Secure Telemetry Tracking and Command (TT&C) Link can be affected by High Power Intentional Jammer Attack (J/S=30dB) or Cryptographic Attack jointly with Low signal to Noise Ratio (SNR ≥ -25dB) and Large Frequency Doppler (F D =60KHz).  Needs: To cope with Jamming and Cryptographic attack, a very Long Cryptographic PN Codes are suggested for Spread Spectrum TT&C Communications for both GSO, MEO and LEO Satellite Mission Scenarios  Challenge: Very Long PN Codes On-board Synchronization, in presence of High jamming Power Interference, CDMA Users, Low SNR and large Frequency Doppler  Proposed Solution: A new On-board Blind Synchronizer Architecture for GSO-MEO and LEO Scenarios based on Fast Acquisition Techniques for Very Long PN Codes

Frequency Domain Correlation Technique Overview Fast Acquisition of a very long PN Code in Low Signal to Noise ratio with high doppler and doppler rate and high jammer over signal power ratio (J/S) The correlation between the Up-link PN code and the Local one is performed in frequency domain exploiting the following relationship:                    N 1    * True only for N-Periodic signal R m x r * x r m IFFT FFT x r FFT x r  UP Local UP Local r 0 The Long Up-link PN Code is a non-periodic signal (N<<Up Link code length) Zero Padding Method N   (N-L) Up/L samples L zeros x r     Up / L             * R m IFFT FFT x r FFT x r    UP Local ZP N Local-samples L 1 x Local r Only the first L+1 samples of the IFFT are preserved (IFFT) L+1 , discarding the others

On-Board Synchronizer Architecture Jammer In-Phase Up-Link Signal block J/S>0 I Mitigation Algorithm N-L L Digital Front-End A C + F IF I+j*Q Block  Doppler >T T ADC Threshold Resize FFT* IFFT Compensation Test (T T ) J/S<0 (L+1) W D Q + <T T N-L L F S Quadrature Up-Link Signal block Code Parallel Searching Capability: Tracking F S /2 B L +1 Code Phases R C_ACQ Local PN N FFT Code Gen On Board Code Shift = (L +1) Code Phases On Board Local Code Block ASIC N = Incoming and Local Block Size (samples) L = Zero Padding Length (samples) ASIC/FPGA D =Doppler Compensation Sub-ranges N =8192 samples=4071 chips W =Non-Coherent Integration length R C_ACQ = Local Code Rate during Acquisition L ~ 6500÷7000 samples=3250÷3500 chips F S =Sampling Frequency=4R C R C =Code rate F IF =Intermediate Frequency F S =Sampling Frequency

Doppler Compensation Technique Up-Link Doppler IFFT FFT* Code Compensation Local FFT Code To compensate the effect of the Up Link Carrier Frequency Doppler shift, the FFT* output circular shifting by a suitable amount of samples can be exploited: Fourier Transform – Frequency Shifting Property Discrete Time Domain:  2      N j id             N    x i e X k d j 2 i f t x t e X f f d Up / L Up / L d   : x i Input Sequence of length “N” Up / L m module N operation m : N Any carrier frequency Doppler effect can be compensated by means of the circular rotation of the FFT result according to the frequency compensation resolution, given by: f   s f (f s is the sampling frequency, N is the length of the input sequence) N The Loss due to the uncompensated carrier Doppler Frequency shift f d is determined by:       2 (T CI is the pre-detection integration time) L sin c f T dop dop CI

Doppler Compensation Technique  2           N j i DS n     N x i e X k DS n Up / L  Doppler f Subrange  Overlap f _ subrange DS=-1 DS=0 DS=1 DS=-(D-1)/2 DS=(D-1)/2 Freqeuncy Doppler -F 2 =-n*FFT RES F 2 =n*FFT RES F DS =-DS*n*FFT RES F DS =DS*n*FFT RES  The Whole Up Link Carrier Frequency Doppler range ( ) is partitioned into “D” partially f overlapped Doppler Subranges (DS) which are tested serially over time by means of different FFT* output circular shifting:       D 1 D 1    DS ,.. 1 , 0 , 1 ... , ( D odder ) 2 2 In order to compensate the DS th Doppler Subrange, the FFT* is circularly shifted by: DS  n samples n is the minimum FFT samples shifting, designed based on the maximum Doppler allowed by synchronization algorithm without Doppler Compensation

Jammer Mitigation Algorithm Jammer J/S>0 The aim of the Jammer Mitigation Algorithm is to Mitigation Algorithm aid the useful correlation peak detection in a very hostile environment (jammer with large J/S).  IFFT L Out Threshold >T T Test (T T ) J/S<0 W The Output of the “Non Coherent Integrator ” is circularly <T T shifted and then subtracted from its original version as show below: On Board Code Code ------ 2 1 L L+1 Non coherent accumulator Output Shift (L+1)samples Tracking - ------ L+1 1 L-1 Circularly shifted Non coherent accumulator Output L = ------ 1-L+1 2-1 L-L+1 L+1-L Jammer Mitigation Block Output 4 Jammer Mitigation Algorithm Output - Input J/S=38dB 4 NCI Output x 10 x 10 3.5 4 3 3 2.5 2 Jammer Mitigation 2 Correlation Magnitude Correlation Magnitude 1 Algorithm 1.5 0 1 -1 0.5 -2 0 -0.5 -3 -1 -4 -1.5 0 1000 2000 3000 4000 5000 6000 7000 -5 0 1000 2000 3000 4000 5000 6000 7000 Correlation Samples Correlation Samples

On Board Synchronizer Architecture Mathematical Overview Jammer In-Phase Up-Link Signal block J/S>0 I Mitigation Digital Front-End L N-L C A + I+j*Q F IF Block  Doppler >T T Threshold ADC IFFT FFT* Resize Compensation Test (T T ) J/S<0 W (L+1) Q + <T T N-L L F S Parallel Searching Capability: Quadrature Up-Link Signal Code L +1 Code Phases block Tracking B F S /2 R C_ACQ Local PN N FFT Code Gen On Board Code Shift = (L +1) Code Phases On Board Local Code Block Algorithm Main Key Parameters:  Correlation peak expected value: •Incoming and Local Block Size “N” (samples) = FFT Length     N  2 2 L •Zero Padding Length “L” (samples)  Maximum allowed Carrier Frequency Doppler •Non Coherent Integration Length “W ” without compensation: F  Max s f  ,   Maximum Non coherent Integration length “W” to keep down   Doppler 2 N L to ¼ chip the codes sliding and avoid to compensate the code  Parallel Searching Capability: L [ samples ] doppler effect:    F F   * S Carrier   W W          2 N L f 4 R  C   f max Link Freq . Doppler Shift

Synchronizer Architecture- Correlation Peak Detection example Jammer In-Phase Up-Link Signal block J/S>0 I Mitigation Digital Front-End L N-L C A + I+j*Q F IF Doppler Block  Threshold >T T ADC FFT* Compensation IFFT Resize Test (T T ) J/S<0 W D Q (L+1) + <T T L N-L F S On Board Code Shift = (L +1) Code Phases Quadrature Up-Link Signal Code block Tracking B F S /2 R C_ACQ Local PN N FFT Correlation-Peak Code Gen 140 On Board Local Code Block 120 100 N=8192 [samples], 4096 [chips], ( Sample block size) 80 L=6890 [samples], 3445 [chips], (Zero Padding length) Correlation Peak 60 W=30, (non coherent Integration length) 40 R C =4Mcps,(Code Rate) 20 F IF =130MHz, (Receiver Intermediate Frequency) F s =40MHz (Sampling Frequency) 0 Code offset simulated=1999 samples=999.5 chips -20 Correlation peak index=1999 (Simulation Result) -40 0 1000 2000 3000 4000 5000 6000 7000 Samples Up Link Carrier Doppler= +471KHz, S/N 0 =45dBHz ( SNR=-24dB) Codes misalignment=2000 samples