Fail-Safe Strategies for FPGA Devices Targeted for Critical Applications Melanie Berg, AS&D in support of NASA/GSFC Melanie.D.Berg@NASA.gov Kenneth LaBel, NASA/GSFC Jonathan Pellish, NASA/GSFC Presented by Melanie Berg at the Single Event Effects (SEE) Symposium and Military and Aerospace Programmable Logic Devices (MAPLD) Workshop, 1 May 18-21, 2015, San Diego, CA.
Acknowledgements • Some of this work has been sponsored by the NASA Electronic Parts and Packaging (NEPP) Program and the Defense Threat Reduction Agency (DTRA). • Thanks is given to the NASA Goddard Radiation Effects and Analysis Group (REAG) for their technical assistance and support. REAG is led by Kenneth LaBel and Jonathan Pellish. Contact Information: Melanie Berg: NASA Goddard REAG FPGA Principal Investigator: Melanie.D.Berg@NASA.GOV Presented by Melanie Berg at the Single Event Effects (SEE) Symposium and Military and Aerospace Programmable Logic Devices (MAPLD) Workshop, 2 May 18-21, 2015, San Diego, CA.
Acronyms • Application specific integrated circuit (ASIC) Mean time to failure (MTTF) • • Block random access memory (BRAM) • Operational frequency ( fs) • Block Triple Modular Redundancy (BTMR) • Power on reset (POR) • Clock (CLK or CLKB) • Place and Route (PR) • Combinatorial logic (CL) • Radiation Effects and Analysis Group (REAG) • Configurable Logic Block (CLB) • Single event functional interrupt (SEFI) • Digital Signal Processing Block (DSP) • Single event effects (SEEs) • Distributed triple modular redundancy (DTMR) • Single event latch-up (SEL) • Edge-triggered flip-flops (DFFs) • Single event transient (SET) • Equivalence Checking (EC) • Single event upset (SEU) • Error detection and correction (EDAC) Single event upset cross-section ( σ SEU ) • • Field programmable gate array (FPGA) • Static random access memory (SRAM) • Gate Level Netlist (EDF, EDIF, GLN) • System on a chip (SOC) Global triple modular redundancy (GTMR) • • Hardware Description Language (HDL) • Input – output (I/O) • Linear energy transfer (LET) • Local triple modular redundancy (LTMR) • Look up table (LUT) Presented by Melanie Berg at the Single Event Effects (SEE) Symposium and Military and Aerospace Programmable Logic Devices (MAPLD) Workshop, 3 May 18-21, 2015, San Diego, CA.
Agenda • Single Event Upsets (SEUs) in FPGAs and Fail-Safe Overview. • Single Event Upsets and FPGA Configuration. • Single Event Upsets in an FPGA’s Functional Data Path and Fail-Safe Strategies. • Fail-Safe Strategies for FPGA Critical Applications. • Fail-Safe State Machines. Presented by Melanie Berg at the Single Event Effects (SEE) Symposium and Military and Aerospace Programmable Logic Devices (MAPLD) Workshop, 4 May 18-21, 2015, San Diego, CA.
SEUs and FPGAs • Ionizing particles cause upsets (SEUs) in FPGAs. • Each FPGA type has different SEU error signatures: – Temporary glitch (transient), – Change of state (in correct state machine transitions), – Global upsets: Loss of clock or unexpected reset, – Route breakage (no signal can get through), and – Configuration corruption. • The question is how to avoid system failure and the answer depends on the following: – The system’s requirements and the definition of failure, – The target FPGA and its surrounding circuitry susceptibility, – Implemented fail-safe strategies, – Reliable design practices, – Radiation environment, and – Trade space and decided risk. Presented by Melanie Berg at the Single Event Effects (SEE) Symposium and Military and Aerospace Programmable Logic Devices (MAPLD) Workshop, 5 May 18-21, 2015, San Diego, CA.
SEUs and FPGA Variations • FPGA susceptibilities (error signatures) vary per FPGA type. • How does a project manage and protect against FPGA SEU susceptibilities? (schemes will change based on FPGA type). • The most efficient solution will be based on understanding: – SEE theory, – FPGA SEE susceptibility (per FPGA type), – Proven mitigation strategies per FPGA type, – Validation and verification of implemented mitigation strategies, and – Limitations of tools and/or mitigation schemes. Consideration: when and how should mitigation be added to a design Presented by Melanie Berg at the Single Event Effects (SEE) Symposium and Military and Aerospace Programmable Logic Devices (MAPLD) Workshop, 6 May 18-21, 2015, San Diego, CA.
Radiation Hardened (per SEU) versus Commercial FPGA Devices • A radiation hardened (per SEU) FPGA is a device that has embedded mitigation. • Radiation hardened FPGA devices are available to users. They make the design cycle much easier! • They are considered hardened if: – Configuration susceptibility is reduced to an acceptable rate. – Generally, less than one node per 1x10 -8 days. – Be careful: with millions of nodes, this can translate into 1 or two configuration failures per year. – However, if the node isn’t being used, then your circuit may not be affected by the failure. • Radiation hardened devices are expensive. The trade: use a radiation hardened device verses manually inserting mitigation into a commercial device . Presented by Melanie Berg at the Single Event Effects (SEE) Symposium and Military and Aerospace Programmable Logic Devices (MAPLD) Workshop, 7 May 18-21, 2015, San Diego, CA.
Radiation Hardened versus Commercial FPGA Device Geometries And Gate Count As Geometries Get Smaller, More Gates Are Available for Mitigation Courtesy of Synopsys Virtex UltraScale+ 16nm Kintex UltraScale+ 16nm Virtex UltraScale 20nm Kintex UltraScale 20nm Virtex-7 28nm Virtex-7Q 28nm Stratix 5 65nm Virtex 5 65nm Virtex 5QV 65nm Virtex 4QV and Virtex 4 90nm RT-ProASIC 130nm RTAX-S 150nm 0 1 2 3 4 5 = SEU Hardened/Harder Logic Capacity - Millions Presented by Melanie Berg at the Single Event Effects (SEE) Symposium and Military and Aerospace Programmable Logic Devices (MAPLD) Workshop, 8 May 18-21, 2015, San Diego, CA.
FPGA Devices Listed by Configuration Type (Not All Are Included in The List): Embedded Mitigation Manufacturer Configuration Short List of Embedded Type Device Families Mitigation Altera SRAM Stratix No Microsemi Antifuse RTAX, RTSXS Clocks +DFFs (configuration is already hardened by nature) Microsemi Flash ProASIC3 Configuration is already hardened by nature. Xilinx SRAM Virtex, Kintex No Xilinx Hardened SRAM Virtex V5QV Configuration + DICE DFFs + SET filters Go to http://radhome.gsfc.nasa.gov, manufacturer websites, and other space agency sites for more information on SEU data and total ionizing dose data. Presented by Melanie Berg at the Single Event Effects (SEE) Symposium and Military and Aerospace Programmable Logic Devices (MAPLD) Workshop, 9 May 18-21, 2015, San Diego, CA.
FPGA Devices Listed by Configuration Type (Not All Are Included in The List): Susceptibility Configuration Type Short List of Embedded Most Susceptible Device Families Mitigation Components SRAM Stratix, Virtex, No Configuration Kintex Antifuse RTAX, RTSXS DFFs and clocks Combinatorial logic (configuration is (however already hardened by susceptibility nature) considered low) Flash ProASIC3 Configuration is DFFs and clocks already hardened by nature. Hardened SRAM Virtex V5QV Configuration + Clocks. In some DICE DFFs + SET cases additional filters mitigation may be necessary for Go to http://radhome.gsfc.nasa.gov, manufacturer configuration and websites, and other space agency sites for more DFFs information on SEU data and total ionizing dose data. Presented by Melanie Berg at the Single Event Effects (SEE) Symposium and Military and Aerospace Programmable Logic Devices (MAPLD) Workshop, 10 May 18-21, 2015, San Diego, CA.
FPGA Structure Categorization as Defined by NASA Goddard REAG: Radiation effects and analysis group(REAG); Single event functional interrupts (SEFI); SEFI out of presentation scope. SEU cross section: σ SEU Design σ SEU Configuration σ SEU SEFI σ SEU Functional logic σ SEU Sequential (DFF) Global Routes and Combinatorial and Hidden logic (CL) in data Logic path SEU Testing is required in order to characterize the σ SEU s for each of FPGA categories. Presented by Melanie Berg at the Single Event Effects (SEE) Symposium and Military and Aerospace Programmable Logic Devices (MAPLD) Workshop, 11 May 18-21, 2015, San Diego, CA.
Preliminary Design Considerations for Mitigation And Trade Space Determine Most Susceptible Components: • Does the designer need to add mitigation? • Will there be compromises? – Performance and speed, – Power, – Schedule, – Reliability: • Are you mitigating the susceptible components? • Is the design working and mitigating as expected? Impact to speed, power, area, reliability, and schedule are important questions to ask. Presented by Melanie Berg at the Single Event Effects (SEE) Symposium and Military and Aerospace Programmable Logic Devices (MAPLD) Workshop, 12 May 18-21, 2015, San Diego, CA.
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