Embedded Control Systems Samarjit Chakraborty www.rcs.ei.tum.de TU - PowerPoint PPT Presentation

Embedded Control Systems Samarjit Chakraborty www.rcs.ei.tum.de TU Munich, Germany Joint work with Dip Goswami (now at TU/e), Reinhard Schneider (now at Audi), Wanli Chang (now at Singapore Institute of Technology), Anuradha Annaswamy (MIT), Arne Hamann (Bosch), and many others ... Technische Universität München Technische Universität München

Control Systems Design Equations system model controller System Controller Control system identification design analysis 2 Technische Universität München

Control Systems Implementation Equations system model controller System Controller Control system identification design analysis Software Task Code Message Task mapping partitioning generation scheduling & scheduling NO Timing & performance Are control analysis objectives satisfied 3 Technische Universität München

The Design Flow Controller Design system model controller System Controller Control system identification design analysis Controller Implementation Task Code Message Task mapping partitioning generation scheduling & scheduling NO Timing & performance Are control analysis objectives satisfied 4 Technische Universität München

The Design Flow Controller Design Design assumptions § Infinite numerical accuracy § Computing control law takes negligible time § No delay from sensor to controller § No delay from controller to actuator Control theorist § No jitter § … Controller Implementation Implementation reality § Fixed-precision arithmetic § Tasks have non-negligible execution times § Often large message delays § Time- and event-triggered Embedded systems communication engineer 5 Technische Universität München

The Design Flow Controller Design These are implementation details Not my problem! Control theorist Controller Implementation Model-level assumptions are not satisfied by implementation Embedded systems engineer 6 Technische Universität München

Semantic Gap Controller Design Semantic gap between model and implementation Controller Implementation Research Questions? § How should we quantify this gap? § How should we close this gap? Solution: Controller/Architecture Co-design 7 Technische Universität München

Resource-aware Controller Design stability, settling time, Controller Design peak overshoot, ... computation, communication Implementation Platform memory, power, ... § Traditionally, Computer Science has been concerned with efficient implementation of algorithms § What are notions of efficiency? Computation, communication, memory, energy, ... § Metrics for control algorithms have been different ... 8 Technische Universität München

Control Tasks - Characteristics The deadlines are usually not hard for control-related messages DC motor: Objective: A fraction of feedback signals being dropped 70 33% Drop 25% Drop 60 0% Drop 50 Controllers can be 40 Speed designed to be robust to drops and deadline-misses 30 20 10 0 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Seconds 9 Technische Universität München

Control Tasks - Characteristics Sensitivity of control performance depends on the state of the controlled plant 50 (1) The computation requirement at the 45 steady state is less, i.e., sampling 40 frequency can be reduced (e.g., 35 event-triggered sampling) 30 Speed h =20ms h =200ms 25 (2) The communication requirements are Disturbance 20 less at the steady state, (e.g., lower 15 priority can be assigned to the 10 feedback signals) 5 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Seconds 10 Technische Universität München

Bottomline • Embedded and Real-time Systems • Meeting deadlines is the center of attraction • Co-design • Deadline takes the back seat • As a result, the design space becomes bigger • Resulting design is better, robust, cost-effective … • Design objectives shift from “lower level” metrics like deadlines to metrics governing system dynamics (like stability) 11 Technische Universität München

What about NCS? T 3 T 4 m 2 m 3 T 2 + Plant Controller - Network m 1 Sensor T 1 Networked Control Systems • Take network characteristics into account when designing the control laws • Packet drops, delays, jitter … 12 Technische Universität München

What about NCS? Answer: ANCS T 3 T 4 m 2 m 3 T 2 + Plant Controller - Network m 1 Sensor T 1 Arbitrated Networked Control Systems • ANCS – We can design the network • By taking into account control performance constraints • Problem: How to design the network? • Given a network, how to design the controller? • NCS problem • Co-design Problem: How to design the network and the controller together? 13 Technische Universität München

A Simple Case 14 Technische Universität München

Controller Design: Continuous Model • We have a linear system given by the state-space model • For n-dimensional Single-Input-Single-Output (SISO) systems • Objective • u = ? 15 Technische Universität München

Controller Design: Continuous Model • Control law r = reference K = feedback gain F = static feedforward gain • How to design K? • How to design F? 16 Technische Universität München

Computing Feedback Gain • Choose the desired closed-loop poles at • Pole placement is a constrained optimization problem (poles: decision variables, objective: control performance, constraints: saturation, stability) • Using Ackermann’s formula we get • Poles of (A+BK) are at 17 Technische Universität München

Static Feedforward Gain Closed-loop system Taking Laplace transform F should be chosen such that y(t) ! r (constant) as t ! 1 i.e., Using final value theorem 18 Technische Universität München

Digital Platform: Sample and Hold Processor clock u(t k ) x(t k ) x(t) u(t) Continuous-time Sampler D/A A/D Hold system Control Algorithm D/A ! digital-to-analog converter A/D ! analog-to-digital converter • Input u(t) is piecewise constant • Look at the sampling points 19 Technische Universität München

ZOH Sampling x(t) t ! Sampling period = h x(t k ) t k t k+1 t k+2 u(t) t ! 20 Technische Universität München

Design: Step 1 (Discretization) ZOH periodic sampling with period = h 21 Technische Universität München

Design: Step 2 (Controller Design) Objectives • Given system: (i) Place system poles (ii) Achieve y ! r as t ! 1 (iii) Design K and F • Control law: 1. Check controllability of ( φ , Γ ) ! must be controllable. γ must be invertible. 2. Apply Ackermann’s formula 3. Feedforward gain 22 Technische Universität München

Step 2 • Given • The control input such that closed-loop poles are at • Using Ackermann’s formula: 23 Technische Universität München

Continuous Vs Discrete Time Continuous-time ZOH periodic sampled Input: Input: Controllability matrix: Controllability matrix: 24 Technische Universität München

The Real Case Feedback loop Loop start T m : measure u = K*[x1(i);x2(i)] + r*F; xkp1 = phi*[x1(i);x2(i)]+ Gamma*u; T c : compute x1(i+1) = xkp1(1); x2(i+1) = xkp1(2); Loop end T a : actuate T m sensor task T c controller task T a actuator task 25 Technische Universität München

Control Loop Feedback loop Sensor reading τ = sensor-to-actuator delay T m : measure T m T c : compute T c T a : actuate T a h= sampling period Actuation Ideal design assumes: or 26 Technische Universität München

Control Task Triggering • In general, T m and T a tasks consume negligible computational time and are time-triggered • T c needs finite computation time and is preemptive • When multiple tasks are running on a processor, T c can be preempted T m T c T a τ τ τ τ Sensor-to-actuator delay: τ 27 Technische Universität München

Control Task Model: Constant Delay preemption wait T c Deadline D c T m T m T a Sampling period = h 28 Technische Universität München

Design Steps Real-time tasks + control applications Task models Overall response time analysis Stage I Partial redesign Schedulability test +Timing properties Controller design Stage II Design objectives met? No Yes 29 Technische Universität München

Bus Arbitration Policies Processor 1 Processor 2 Processor 3 Communication Bus When multiple processors want to transmit data at the same time, how is the contention resolved? • Using a bus arbitration policy, i.e., determine who gets priority • Examples of arbitration policies • Time Division Multiple Access (TDMA) • Round Robin (RR) • Fixed Priority (FP) • Earliest Deadline First (EDF), … 30 Technische Universität München

Time Vs Event-Triggered Arbitration Processor 1 Processor 2 Processor 3 Communication Bus Time-triggered arbitration policy: P1 P2 P3 P1 P2 P3 time Bus period All components have a priory knowledge of the message send/ receive time instants (global time) 31 Technische Universität München

Time Vs Event-Triggered Arbitration Processor 1 Processor 2 Processor 3 Communication Bus Event-triggered arbitration policy: P2 preempted by P1 P2 resumes Priority: execution P1 > P2 > P3 P2 P1 P2 P3 time 32 Technische Universität München