EEC 181 Design Plan By: Christopher Bacchi, Andrea Lopez, Krysteen - PowerPoint PPT Presentation

EEC 181 Design Plan By: Christopher Bacchi, Andrea Lopez, Krysteen Terlouw

Algorithm Flowchart

Software Profiling Runtime Stage Runtime (%) 1 84 2 12 3 4 Within Stage 1, the inner loop takes 90% of the runtime.

Hardware RTL Block Diagram

Task Implementations Software Interface Hardware • Data Compression • PIOs • Node Matrix Multiplication • Sigoid function • FPGA SDRAM • Summing computation • FPGA On CHip • Maximum/final answer computation

Memory Resources & Usage Weights and Bias Data Image Data Computational Compression Results • Stage 1 & 2 Weight Reduction: • Test Data Reduction: 291kB + 48 kB 7.9MB → 826 kB • FPGA On Chip (5x less) (10x less) memory remaining: 281 kB • Stage 1&2 Bias Reduction: • Resources Needed: 2kB → 1kB 826 kB • Immediate computations and • SoftMaxTheta: • HPS SDRAM: results stored in FPGA 4kB 64MB On chip memory • Resources Needed: • After data is processed, it will 344kB not move or be rewritten during the entire algorithm. • FPGA On Chip memory: 625 kB

Performance Prediction COMPONENT HPS CUSTOM ONCHIP SDRAM COMPONENT MEMORY TIME Process & write X X X Readin NN data X X X start loop thru & wb X X progess sigoid & X X loop to next stage finish all stages & X X loop to next image