ECON ASICs Gregory Deptuch, Zoltan Gecse, Jim Hirschauer, Sandeep Miryala, Paul Rubinov ASICs PMG 10 May 2019
Reminders • Two Endcap Concentrator (ECON) ASICs on independent data paths: • ECON-TRG : select and compress interesting data for transmission off detector at 40 MHz. • ECON-DAQ : perform zero suppression and concentrate for events passing L1 trigger at 750 kHz. • Baseline architecture : • ECON-T : 36x 1.28 Gbps inputs + 3x 10.24 Gbps inputs • ECON-D : 36x 1.28 Gbps inputs + 7x 1.28 Gbps inputs • Baseline schedule : • ECON prototype 1 : • verify essentially all ECON pieces except internal algorithms including high speed I/O, power distribution, PCB/package interface, etc. • ECON prototype 2 : • incorporate trigger algorithm for ECON-T • incorporate zero suppression logic and smart buffer for ECON-D • Need to submit by June 2020 to be ready for full system test • ECON production : full production of both ECON-T and and ECON-D 2
Recent developments • CD-1 Director's Review • Comment : We are worried that, as currently envisioned, the first prototype of the ECON concentrator ASIC will take much longer to design than anticipated and will still have a significant risk of failure. We believe it would be safer to first design a prototype with 36 1.28 Gbps inputs and 7 1.28 Gbps outputs. This is the configuration required for ECON-D, and this configuration could also be used for ECON-T, albeit at the cost of a more complex printed circuit board design requiring more LpGBTs. • Recommendation : Consider the approach described above for the ECON ASICs to reduce schedule and performance risks. • Optimization of motherboard / system design: • CMS has been become more concerned about high multiplicity of motherboard variants. • System design options that reduce motherboard variety impact optimal ECON design. • ECON schedule: • Despite excellent progress, latest forecast shows ECON P1 submission moving from Aug ➔ Dec 2019. Evolving ECON plan* must address all of these developments. * all plans are necessarily evolving plans 3
ECON internal mini-review on May 14 Goals: • Finalize ECON architecture choices. • Present status and plans for ECON design in more technical detail than possible during usual HGCAL meetings. ECON presenters • Gregory, Sandeep, Ralph Wickwire, Mike Hammer (ANL), Ante Kristic (Split), Paul Rubinov, Hirschauer Reviewers: • Magnus Hansen (CMS electronics coordinator), Paolo Moreira and Szymon Kulis (lpGBT designers) • HGCAL people : Paul Aspell, Sandro, etc. 4
Optimization of motherboard / system design • Modules (yellow/green on right) in each 60° sector of each layer are connected and readout by motherboards (gray on right). • M odules hold HGCROCs • M otherboards hold ECONs, optical transmitter(s), etc. • With 51 layers of varying module arrangement and varying required bandwidth, the tendency towards a high multiplicity of motherboard variants is evident . • Minimization of this multiplicity is one contribution to multi-dimensional optimization 5
System design : illustration of two approaches Total: # DAQ/TRG 12/12 12/12 6/12 elinks 30/36 Maximal concentration D T L V 36x1G in motherboard (3/1)x10G out engine 12/12 12/12 6/12 Staged compression L L D D D T T T V +serialization L L 12x1G in 12x1G out engine many varieties of few varieties of simple passive few varieties of complex transmitter connection boards complex ECON boards boards 6
Advantages / Disadvantages of two approaches Maximal Staged concentration compression+serialization 36x1G in 12x1G in (3/1)x10G out 12x1G out • Simpler 2-chip engine • More naturally allows isolation of complexity into • ECON board • more flexible load balancing • Transmitter board • t ransmitter redundancy Advantages • N aturally accommodates FPGA ECON emulator board • ~20% lower power for system early prototyping • Less ECON design time • More unified ECON-D / ECON-T architectures • Lower risk of ECON prototype problems • Simpler / less expensive ECON package • decentralization lowers single point failure risk • Longer ECON design time • More dense 4-chip engine • Higher risk of ECON • Less flexible load balancing Disadvantages prototype problems • Single point failure 7
ECON development schedules for two approaches CMS need-by dates for System Test and Final chip • Compare schedules for 12in-12out and 36in-(3/1)out ST ST FC ST FC • Conclusion 12in-12out plan allows for delivery ~6 months sooner than 36in-(3/1)out 8
Message for ECON May 14 review • In the past weeks, Fermilab ECON designers and system designers have considered the diverse aspects of ECON and HGCAL system design optimization including: • System / PCB complexity (and associated schedule risks, technical risks, and cost) • ASIC and package complexity (and associated schedule risks, technical risks, and cost) • power requirements • link counts (which drives cost) • readout redundancy and flexibility • ease of system prototyping • Taken all together, we conclude that the 12in-12out ECON design with the associated modular system design offers more advantages than an 36in-(3/1)out ECON design, so we propose to pursue the 12in-12out design. 9
To do for May 14 and May 20 P2UG • JH : finalize link count comparison • JH : update power estimates • JH & GD : provide CMS with intermediate ECON design milestones for Sep 2019 and Jan 2020 • All : finalize talks (drafts have already been reviewed) 10
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