Duo-Binary Circular Turbo Decoder Based on Border Metric Encoding - PowerPoint PPT Presentation

Duo-Binary Circular Turbo Decoder Based on Border Metric Encoding for WiMAX for WiMAX Ji-Hoon Kim and In-Cheol Park Division of Electrical Engineering Division of Electrical Engineering KAIST

Introduction to Turbo Codes Introduction to Turbo Codes • Introduced in 1993 – Error Correcting Performance within 0.5dB of Shannon limit – Widely Used in W-CDMA, CDMA2000, and WiMAX Wid l U d i W CDMA CDMA2000 d WiMAX – Non-Uniform Interleaver – Iterative Decoding Iterative Decoding RSC SISO Encoder 1 Decoder 1 Interleaver Interleaver RSC SISO Encoder 2 Decoder 2 2

Turbo Codes for WiMAX Turbo Codes for WiMAX • Double-Binary Turbo Codes • Circular Coding – Better Convergence – a.k.a Tail-Biting – No Tail Bits No Tail Bits – Larger Minimum Distances Larger Minimum Distances – Reduced Latency – Avoid Spectrum Waste < CTC Encoder for WiMAX > < 4-State Trellis for Circular Coding > 3

Max log MAP for Double Binary Max-log-MAP for Double-Binary Z (Source Bits) 7 7 11/00/01/10 6 6 01/10/11/00 5 5 11/00/01/10 4 4 01/10/11/00 3 3 10/01/00/11 2 2 00/11/10/01 1 1 10/01/00/11 with Minimum Overhead with Minimum Overhead 0 0 00/11/10/01

Sliding Window For Non-Binary Turbo Decoder • Border Metric with the values Small Window Size, of previous Iteration Large Frame Size � Huge Border Memory! g y – Avoid complex dummy calculation Avoid complex dummy calculation Complex Efficient for Efficient for Efficient for Efficient for Dummy Metric Calculation Dummy Metric Calculation Circular Coding Circular Coding @ Border

Proposed Border Metric Encoding Proposed Border Metric Encoding • Allow only a few values for the Border Metric Flooring the Original Value to the Closest Power-of-Two Number Encoding Scheme Encoded Values ± 256, ± 128, ± 64, ± 32, ± 16, ± 8, ± 4, 0 4-bit Encoding (15 values) 6

BER Performance Comparison BER Performance Comparison • Almost No Performance Degradation! 7

Proposed Dedicated Interleaver Proposed Dedicated Interleaver • Accumulator-Based Interleaver – Small Area due to Simple Hardware 8

Key to Low Power Consumption Key to Low-Power Consumption • Small-Sized Border Memory – By Border Metric Encoding • Infrequent Access to Border Memory I f t A t B d M – Only one load/store for processing one Window 9

Implementation Results Implementation Results • Time Multiplex Architecture • Time-Multiplex Architecture Max-log-MAP Operating SISO Algorithm 200 MHz (Duo-Binary) Frequency Window Size 32 Iteration 8 (Fixed) Gate Count 65k Data Rate 24.26 Mbps

Memory Size Comparison Memory Size Comparison • Single-Port SRAM Size – Required for a SISO Decoder 100 % 100.4 % 20.7 % 79.3 % 11

Energy Consumption Comparison Energy Consumption Comparison • For a SISO Decoder @ 1 2dB • For a SISO Decoder @ 1.2dB 100 % 26.2 % 73.8 % 12

Conclusion Conclusion • Border Metric Encoding is Proposed – Avoid Complex Dummy Calculation – Effective for non-binary Turbo Codes Eff ti f bi T b C d • Dedicated Hardware Interleaver is Proposed – Generate Interleaved Addresses on-the-fly • CTC Decoder for WiMAX is Designed g – Based on .. • Border Metric Encoding • Dedicated Hardware Interleaver 13