Development of 3D Integrated Circuits for HEP R. Yarema Fermi National Accelerator Lab Batavia, Illinois 12 th LHC Electronics Workshop, Valencia, Spain September 25-29, 2006
Outline • Brief overview of IC development from MAPS to SOI Detectors to 3D ICs. • Present several examples of 3D imaging arrays. • Discuss technologies used for 3D • Present ILC vertex detector requirements. • Present a 3D readout chip based on ILC vertex needs. 12th LHC Electronics Workshop 2
Introduction • Requirements for HEP front end electronics and detectors continue to push the limits for lower mass and power, and higher resolution. • One example is pixel vertex detectors • Multiple scattering in the detector and the readout electronics limits the precision of particle track reconstruction – Therefore very low mass is required. – Because low mass is necessary, there is little room for cooling material and hence low power is needed. – High resolution requires smaller pixels which increases the readout circuit density. • Significant progress has been made in the last decade to address these issues by integrating sensors and front end electronics within the pixel cell – Monolithic Active Pixel Sensors – SOI Pixel Sensors – Recent developments in 3D circuits • Offers improved performance over other approaches for HEP and other related applications. 12th LHC Electronics Workshop 3
MAPS Development • Monolithic Active Pixel Sensors have generated a lot Sensing Diode Metal layers of interest and excitement in Polysilicon - + N+ High Energy Physics 1, 2 - + 3 NMOS trans. in pixel N+ Well P+ Well - + – Combine detector and front end - + electronics on same substrate in - + 5-20 um - + a commercial CMOS process P- epi - + (low resistance substrate). - + P++ substrate - + – Some issues Particle • Relatively small signal level Pixel Cross Section (not to scale) • Pixel electronics generally limited to NMOS devices in Pixel reset P-well Pixel output • Limited functionality Diode possible in small pixels sensor • Currently numerous groups Pixel row sel are working on MAPS 3 NMOS transistors in Pixel 12th LHC Electronics Workshop 4
SOI Detector Development • Wafers for SOI detectors Low resistivity wafer are formed by bonding SiO 2 layers for bonding wafers with low and high resistivity using a silicon High resistivity wafer oxide bond. Chemically treat SiO2, apply heat • A buried oxide layer is and pressure formed between the wafers Low resistivity wafer • After bonding, the wafer BOX intended for CMOS High resistivity wafer processing is thinned to a few microns and small vias Thin layer for CMOS are etched through the low CMOS resistivity layer and BOX to Detector High resistivity wafer the high resistivity layer. 12th LHC Electronics Workshop 5
SOI Active Pixel Sensors • SOI APS have advantages over MAPS – CMOS instead of NMOS in pixel – Larger signal proportional to high resistivity substrate thickness. – Less charge spreading 300 um sensor thickness • Early work done in 3 µm process 3 – Large pixels cells not useful for high resolution detectors • Recent work has moved to smaller feature processes => smaller pixels SOI Pixel Cross Section 7 – Collaboration of many groups using the OKI 0.15 µm SOI 4 – Fermilab has an arrangement to work with the ASI (American Semiconductor Inc.) 0.18 µm process and OKI on SOI detector development • SOI offers improved pixel design but still has rather limited functionality within pixel cell. CMOS Transistors in Pixel 7 12th LHC Electronics Workshop 6
3D Integrated Circuit Development • A 3D chip is generally referred to as a chip comprised of 2 or more layers of active Optical In semiconductor devices that have Optical Out been thinned, bonded and Opto Electronics Power In interconnected to form a and/or Voltage Regulation “monolithic” circuit. Digital Layer • Often the layers (sometimes called tiers) are fabricated in Analog Layer 50 um different processes. Sensor Layer • Industry is moving toward 3D to improve circuit performance. Physicist’s Dream – Reduce R, L, C for higher speed – Reduce chip I/O pads – Provide increased functionality – Reduce interconnect power 3D Routing (small chip) 2D Routing (large chip) and crosstalk 12th LHC Electronics Workshop 7
Advantages of 3D for Pixels • Significantly higher functionality in a pixel cell • NMOS and PMOS transistors • Minimal perimeter area requirements • Processing of each layer can be optimized • 3D process is well suited to electronics for pixel arrays Pixel control, CDS, A/D conversion Diode Diode Digital Analog readout Analog readout circuitry circuitry Analog Diode Diode Sensor Analog readout Analog readout circuitry circuitry Conventional MAPS 4 Pixel Layout 3D 4 Pixel Layout 12th LHC Electronics Workshop 8
3D Integrated Circuit Design 3D electronics development is being pursued by many different organizations. Asia: USA: ASET, NEC, University of Tokyo, Albany Nanocenter, AT&T Tohoku University, CREST, BeSang Inc.,IBM, Intel, Fujitsu, ZyCube, Sanyo, Irvine Sensors Toshiba, Denso, Mitsubishi, Sharp, Jazz Semiconductor, Hitachi, Matsushita, Samsung Lincoln Labs, MIT, Micron, RPI, RTI, Sandia Labs Tessera, TI, Tezzaron, U. Of Kansas, Europe: Alcatel Espace, CEA-LETI, EV Group U of Arkansas EPFL, Fraunhofer IZM, IMEC Delft, Vertical Circuits, Ziptronix Infineon, NMRC, Phillips, NMRC, STMicroelectronics, Thales, TU Berlin 12th LHC Electronics Workshop 9
Key Technologies for 3D 5 • Bonding between layers – Oxide to oxide fusion – Copper/tin bonding – Polymer bonding • Wafer thinning – Grinding, lapping, etching, CMP • Through wafer via formation and metalization – With isolation – Without isolation • High precision alignment 12th LHC Electronics Workshop 10
Two Different 3D Approaches for HEP 1) Die to wafer, (or die to die) bonding • Permits easy usage of different processes and different size wafers (SOI+CMOS, CCD+CMOS, DEPFET+CMOS) • Lends itself to using KGD for higher yields 2) Wafer to wafer bonding using SOI • Permits very thin layers for reduced mass – Short, small vias • Layers must align at the wafer level KGD Die to wafer bonding Wafer to wafer bonding 12th LHC Electronics Workshop 11
1) Die to Wafer Approach • Two different types of Face bonding arrangements (circuit) are possible. – 1) Face to back (circuit Die 1 side to substrate side) Face • Inter chip vias Die 2 required for electrical (circuit) interconnection Face to back – 2) Face to face • Inter chip vias not required Die 1 • Examine a couple of bonding arrangements Die 2 for die to wafer approach. Face to face 12th LHC Electronics Workshop 12
Die to Wafer (back to face) 1 2 Handle Polymer Face bond Thinned IC2 Thinned IC2 • Need to leave space in Attach handle + thin IC2 design for vias Pads Face IC1 • Thin die before bonding (1) IC1 IC1 polymer bonded • Polymer bond between parts to IC2, remove handle Add metal pads to IC1 (2) 4 • High aspect ratio via Bosch 3 IC2 IC2 process (3) • Insulated vias needed for IC1 IC1 CMOS (4) Deposit dielectric Etch thru oxide • Low temperature via & clear hole bottom and silicon to pads 5 metalization needed to 6 protect polymer bond (5,6) IC2 IC2 • Variations of this process IC1 IC1 are found in different groups Remove excess metal (copper vias) Fill via 12th LHC Electronics Workshop 13
RTI 3D Infrared Array Example 6 • 256 x 256 array with 30 µm pixels • 3 Tiers – HgCdTe (sensor) – 0.25 µm CMOS (analog) – 0.18 µm CMOS Array cross section (digital) Analog Digital • Die to wafer stacking • Polymer adhesive Analog Components Analog Components Digital Digital Components Components bonding Synchronous Charge Synchronous Charge CLK CLK VCHG VCHG Removal Removal • Bosch process vias (4 µm) with insulated Control Control Cint Cint Logic Logic Cchg Cchg side walls CTIA CTIA OUT OUT + + • 99.98% good pixels + + N Bit N Bit Infrared image Ripple Ripple VRST VRST - - • High diode fill factor Counter Counter - - VTRP VTRP . . . . . . Detector Detector N Bit Parallel N Bit Parallel Analog Residual Analog Residual Digital Data Out Digital Data Out Output Output 3 Tier circuit diagram 12th LHC Electronics Workshop 14
Die to wafer (face to face) • Use copper-tin eutectic bond for electrical and mechanical connection • Possible replacement for bump bonds • In applications to date, the copper interconnect is 10 um thick and covers most of surface area. – Problem for HEP: 10 um Cu => Xo = 0.07% • Fermilab study – Thin FPIX parts (TSMC 0.25 um process) down to 15 microns. Reasonable success for first attempt. – Bond FPIX parts to detectors using Cu+Sn. – Reduce copper coverage to 10% of surface area to minimize Xo for mass critical applications – Attempt 7 um diameter interconnect on 20 um FPIX pitch. 12th LHC Electronics Workshop 15
Fine Pitch CuSn Pillars from RTI for Bonding Along with Cross Section to Show Eutectic Bond 5 micron tall Cu pillars Cross section of bond showing Cu 3 Sn eutectic 12th LHC Electronics Workshop 16
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