DESIGN OF LOW POWER VOLTAGE REGULATOR FOR RFID APPLICATIONS Josip - PDF document

10.12.2015. UNIVERSITY OF ZAGREB FACULTY OF ELECTRICAL ENGINEERING AND COMPUTING DESIGN OF LOW POWER VOLTAGE REGULATOR FOR RFID APPLICATIONS Josip Mikulic Niko Bako Adrijan Baric MIDEM 2015, Bled Overview ♦ Introduction ♦ Voltage Regulator Design ♦ Post-Layout Simulation Results ♦ Experimental Results ♦ Performance Comparison ♦ Conclusion J. Mikulic, N. Bako, A. Baric MIDEM 2015, Bled 2 of 19 1

10.12.2015. Introduction ♦ Industry oriented to full on-chip solutions Profit and production complexity < ♦ Design of the voltage regulators affected Cost production limits chip area < Low-power < Scalability to low voltages < Conventional solutions no longer usable < Fully compensated solutions take advantage < ♦ Topic of this work is the design of voltage regulator which will fulfill the mentioned requirements and will be useable in modern applications, such as RFID J. Mikulic, N. Bako, A. Baric MIDEM 2015, Bled 3 of 19 Voltage Regulator Design Topology Overview ♦ Conventional linear regulator topology Pass device controled by the error amp < Stability ensured with large output capacitor < Area consuming ( C L ) < ♦ Fully compensated linear regulator topology Miller compensation network included < C L no longer important for stability < Area efficient < Convinient for fully integrated solutions = J. Mikulic, N. Bako, A. Baric MIDEM 2015, Bled 4 of 19 2

10.12.2015. Voltage Regulator Design Proposed Topology for the LDO Voltage Regulator ♦ RNMC (Reverse Nested Miller Compensation) error amplifier 1st stage – differential amplifier < 2nd stage – common source < 3rd stage – pass device < VF – direct implementation = of positive gain RNMC topology < Suitable for driving large = capacitive loads with low power VF in a feedback branch = ♦ Feedback network ♦ Decoupling capacitor J. Mikulic, N. Bako, A. Baric MIDEM 2015, Bled 5 of 19 Voltage Regulator Design Open-Loop Transfer Function Analysis ♦ DC gain ♦ Nondominant poles (assuming real) g C ω = ⋅ m 3 C 1 = − A g r g r < p 2 < V 0 m 1 1 m 2 2 C C L C 2 g g ω = mVF m 2 ♦ Dominant pole < p 3 + C g C g C 1 mVF C 1 m 2 1 ω = ♦ Nondominant complex poles ( ) < p 1 ⋅ C g r r C 1 m 2 2 1   ♦ GBW  +  g     2 m 2 4 g C 1   g m 3 C 1     ω = ⋅ ω = g g m 1 A § ω = ± − m 2 mVF 1 j 1 < GBW V 0 p 1   C p 2 , 3  +  g C C g C 1     m 2 L C 2 m 2 2 C 1   ♦ ULGF C 1    g    mVF ω = FB ω ⋅ < ULG GBW r = fb 2 FB < + r r fb 1 fb 2 ♦ Negative Zero g ω = mVF < z C C 1 J. Mikulic, N. Bako, A. Baric MIDEM 2015, Bled 6 of 19 3

10.12.2015. Voltage Regulator Design LDO Voltage Regulator Implementation (I) ♦ LDO voltage regulator designed in 0.18 um CMOS technology Biasing network and power enabling circuitry not shown < 1st stage – differential amplifier < 2nd stage – common source < 3rd stage – voltage follower < Low threshold nMOS = LDO feature = 500 µA = RNMC topology < VF in the feedback branch = Voltage reference < Feedback network < Diode connected transistors = Factor 1/3 = Decoupling capacitor < 100 pF = J. Mikulic, N. Bako, A. Baric MIDEM 2015, Bled 7 of 19 Voltage Regulator Design LDO Voltage Regulator Implementation (II) ♦ Nominal output voltage V OUT : 1.455 V ♦ Nominal quiescent current consumption I Q : 3.7 µA Transistor Size (W/L) I Q M 1 a , M 1 b 1.2µm/1.8µm 0.25 µA M 2 0.96µm/0.54µm 1 µA M 3a 200µm/0.4µm 1.8 µA M VF 0.4µm/1.8µm 0.375 µA M 2 a , M 2 b 0.96µm/3.6µm 0.25 µA M d 1 , M d 2 , M d 3 5.4µm/0.9µm 0.4 µA Capacitor Value M gp 1 1.2µm/1.2µm 0.5 µA C C 1 1.8 pF M gp 2 2.4µm/1.2µm 1 µA C C 2 0.18 pF M gn 1 0.96µm/3.6µm 0.375 µA C L 100 pF M gn 2 0.96µm/5.4µm 1.4 µA J. Mikulic, N. Bako, A. Baric MIDEM 2015, Bled 8 of 19 4

10.12.2015. Voltage Regulator Design LDO Voltage Regulator Implementation (III) ♦ Layout of the designed voltage regulator Area : 0.065×0.085 mm 2 < 0.0055 mm 2 = Output capacitor C L not < shown C C1 0.0129 mm 2 = C C2 M 3 J. Mikulic, N. Bako, A. Baric MIDEM 2015, Bled 9 of 19 Post-Layout Simulation Results Loop Gain AC Response ♦ Simulated loop gain with parameter I L I L : 0 to 500 µA (log steps) < V DD = 1.6 V < GBW = 100 kHz < PM > 75 deg < ♦ Poles and zeros Dominant pole: 0.05 kHz < Nondominant complex poles < Abs. value: 320 kHz to 1.5 MHz = Negative zero: 500 kHz < J. Mikulic, N. Bako, A. Baric MIDEM 2015, Bled 10 of 19 5

10.12.2015. Post-Layout Simulation Results Power Supply Rejection Ratio ♦ Simulated PSRR with the load current I L as a parameter I L : 0 to 500 µA (log steps) < V DD = 1.8 V < ♦ Low frequencies -80 dB < ♦ Intermediate frequencies Worse for larger < load currents Influenced by the output < resistance of the pass device ♦ High frequencies Converges to the ratio of < C L and C DS of the pass device J. Mikulic, N. Bako, A. Baric MIDEM 2015, Bled 11 of 19 Post-Layout Simulation Results Line Regulation ♦ Simulated DC response of the output voltage V OUT to the supply voltage V DD V DD changing from 1.4 V to 1.8 V < I L = 500 µA < ♦ Line regulation ∆ V = OUT LiR < ∆ V DD I L , MAX LiR = 1.25 mV/V < J. Mikulic, N. Bako, A. Baric MIDEM 2015, Bled 12 of 19 6

10.12.2015. Post-Layout Simulation Results Load Regulation ♦ Simulated DC response of the output voltage V OUT to the load current I L I L changing from 0 to 500 µA < Room temperature < Three voltages < ♦ Load regulation ∆ V = OUT LoR < ∆ I L LoR = 1.08 mV/mA < for V DD = 1.6 V at 500 µA J. Mikulic, N. Bako, A. Baric MIDEM 2015, Bled 13 of 19 Post-Layout Simulation Results Transient Simulations ♦ Simulated transient response of the output voltage V OUT to the step load current I L I L changing from 0 to 500 µA < Rise/fall time of t r/f = 1 µs = V DD = 1.6 V < Settling time: 6 µs < J. Mikulic, N. Bako, A. Baric MIDEM 2015, Bled 14 of 19 7

10.12.2015. Experimental Results ♦ Chip fabricated in UMC 0.18 um VDD Microphotograph and measurement < PCB visible in the figures IBIAS VOUT GND ♦ Results: V OUT = 1.49 V < 35 mV higher than nominal = Δ V = 60 mV < I Q = 4.2 µA < Including the voltage reference = and biasing circuitry LiR = 3.5 mV/V < LoR = 2.4 mV/mA at 500 µA < PSRR: -49 dB at DC < and -16 dB at 1MHz J. Mikulic, N. Bako, A. Baric MIDEM 2015, Bled 15 of 19 Experimental Results Transient Measurement ♦ Measured transient response of the output voltage V OUT to the step load current I L I L changing from 0 to 500 µA < rise/fall time of t r/f = 100 ns = V DD = 1.6 V < Simulation results < for the comparison ♦ Comparison Very good < correspondence between the simulations and measurements J. Mikulic, N. Bako, A. Baric MIDEM 2015, Bled 16 of 19 8

10.12.2015. Performance Comparison [5] [6] [7] This work Technology 0.13µm 0.18µm 65nm 0.18µm ♦ Comparison with other Chip area (mm 2 ) NA 0.2236 NA 0.0184 low-power voltage Input voltage (V) >1.4 1.6 to 2 1.1 to 2.5 1.55 to 1.8 Nominal output voltage (V) 1 1.45 1.013 1.455 regulators Referent voltage (V) 0.462 0.505 0.5078 0.485 Good static and dynamic < Supply capability (µA) 4000 50 50 500 behaviour for the Quiescent current (µA) 11.6 0.7 0.064 3.7 (4.2) invested power 0.29 400 130 1.08 (2.4) Load regulation (mV/mA) LDO feature < @4mA @50µA @50µA @500µA Fully compensated < Line regulation (mV/V) 3.1 22 4.06 1.25 (3.5) Suitable for full on-chip -51dB NA -45dB -80dB (-49dB) < PSRR @DC solutions PSRR @1MHz -12dB NA -62dB -20dB (-16dB) Settling time (µs) 7.9 20 NA 6 Load capacitance (pF) 50 1200 NA 100 ♦ References: Compensated YES NO NO YES [5] L. Lijun, K.D. Gannes, K. Fricke, S. Senjuti, and R. Sobot, „Low–power CMOS voltage regulator architecture for implantable RF < circuits,“ in RFID Technology (EURASIP RFID), 2012 Fourth International EURASIP Workshop on, pp. 99-106, 28-27 Sep. 2012. [6] J. Guo and K.N. Leung, „A CMOS voltage regulator for passive RFID tags ICs,“ International Journal of Circuit Theory and < Application, vol. 40, no. 4, pp. 329-340, April 2012. [7] C.C. Liu. Chia-Chin, C. Chen „An ultra-low power voltage regulator for RFID application,“ in Circuits and Systems (MWSCAS), < IEEE 56th International Midwest Symposium on, p.p. 780-783, 4-7 Aug. 2013. J. Mikulic, N. Bako, A. Baric MIDEM 2015, Bled 17 of 19 Conclusion ♦ Topology based on RNMC, suitable for low-power full on-chip voltage is proposed The topology was proposed based on analytic calculations < ♦ LDO voltage regulator is designed by using the proposed topology Circuit is implemented in 0.18 um technology < Layout was drawn < Post-layout static and dynamic simulations are performed < ♦ The designed regulator is fabricated in UMC 0.18 CMOS process Performed silicon measurements show high correspondence with the simulations < J. Mikulic, N. Bako, A. Baric MIDEM 2015, Bled 18 of 19 9