Design and Architectures for Embedded Systems (ESII) Prof. Dr. J. - PowerPoint PPT Presentation

1 ESII: Specification & Modeling Design and Architectures for Embedded Systems (ESII) Prof. Dr. J. Henkel, M. Shafique Prof. Dr. J. Henkel, M. Shafique CES CES - Chair for Embedded Systems Chair for Embedded Systems Karlsruhe Institute of Technology, Germany Karlsruhe Institute of Technology, Germany Today: Specification and Modeling II Today: Specification and Modeling II - Model and system properties Model and system properties - http://ces.itec.kit.edu J. Henkel, M. Shafique, KIT, WS1011

2 ESII: Specification & Modeling Where are we? - models of computation 2, 3, 4, 5 SYSTEM SPECIFICATION 2, 3, 4, 5 SYSTEM SPECIFICATION -Spec languages Optimization Design Space Exploration Design Space Exploration refine -low power, performance, area, reliability ,… -low power, performance, area, reliability, peak temp. … Estimation&Simulation SYSTEM PARTITIONING SYSTEM PARTITIONING -low power, performance, area, reliability, peak temp. … Hardware Hardware Embedded Embedded Middleware, Middleware, Embedded Processor RTOS Design Software Design & Architectures -Synthesis 13 & 14. 13 & 14. 6. Code 6. Code 7. ISA extensions  7. ISA extensions  Scheduling Generation for Special Instructions Embedded embedded IP: Systems 8. ASIPs, Extensible 8. ASIPs, Extensible -PEs Processors -Memories Optimize for Optimize for -Communication 9. DSPs, VLIW 9. DSPs, VLIW -Peripherals -Low Power -Integration -Integration - … - Performance -Prototyping 10 & 11. Reconfigurable 10 & 11. Reconfigurable IC technology -Area - Tape out Processors -Reliability - 12. Multi-Core  future 12. Multi-Core  future http://ces.itec.kit.edu J. Henkel, M. Shafique, KIT, WS1011

3 ESII: Specification & Modeling Outline  Rugby Meta Model Rugby Meta Model  Case Study A Design Project Case Study A Design Project (src: A. Jantsch) http://ces.itec.kit.edu J. Henkel, M. Shafique, KIT, WS1011

4 ESII: Specification & Modeling The Rugby Meta-Model  Abstraction in four domains  Computation  Communication  Time  Data (src: A. Jantsch) http://ces.itec.kit.edu J. Henkel, M. Shafique, KIT, WS1011

5 ESII: Specification & Modeling Example of a hierarchy (src: A. Jantsch) http://ces.itec.kit.edu J. Henkel, M. Shafique, KIT, WS1011

6 ESII: Specification & Modeling Example of an abstraction (src: A. Jantsch) http://ces.itec.kit.edu J. Henkel, M. Shafique, KIT, WS1011

7 ESII: Specification & Modeling Ways to handle complexity (src: A. Jantsch) http://ces.itec.kit.edu J. Henkel, M. Shafique, KIT, WS1011

8 ESII: Specification & Modeling Hierarchy, Abstraction, Domain (src: A. Jantsch) http://ces.itec.kit.edu J. Henkel, M. Shafique, KIT, WS1011

9 ESII: Specification & Modeling Rugby (src: A. Jantsch) http://ces.itec.kit.edu J. Henkel, M. Shafique, KIT, WS1011

10 ESII: Specification & Modeling Domains in Rugby (src: A. Jantsch) http://ces.itec.kit.edu J. Henkel, M. Shafique, KIT, WS1011

11 ESII: Specification & Modeling Computation Domain (src: A. Jantsch) http://ces.itec.kit.edu J. Henkel, M. Shafique, KIT, WS1011

12 ESII: Specification & Modeling An MOS transistor model (src: A. Jantsch) http://ces.itec.kit.edu J. Henkel, M. Shafique, KIT, WS1011

13 ESII: Specification & Modeling A transistor as switch (src: A. Jantsch) http://ces.itec.kit.edu J. Henkel, M. Shafique, KIT, WS1011

14 ESII: Specification & Modeling An AND gate as transistor network (src: A. Jantsch)  Two problems with arbitrary transistor networks:  Output is not defined when input is 0.  Voltage drop between drain and source is relevant but not visible. that means, the model has not enough details in order to describe correctly the desired behavior We can restrict the transistor network to a small number of patterns that Can be combined in arbitrary networks w/o violating assumption of switch-based transistor model http://ces.itec.kit.edu J. Henkel, M. Shafique, KIT, WS1011

15 ESII: Specification & Modeling An Inverter as transistor network (src: A. Jantsch) http://ces.itec.kit.edu J. Henkel, M. Shafique, KIT, WS1011

16 ESII: Specification & Modeling Gate-based abstraction level  1. The primitive elements are defined by simple models, i.e. small truth tables in this case.  2. The primitive elements can be implemented in a wide range of technologies.  3. The model holds even for arbitrarily large networks of primitive elements. (src: A. Jantsch) http://ces.itec.kit.edu J. Henkel, M. Shafique, KIT, WS1011

17 ESII: Specification & Modeling Algorithms, Functions, Relations (src: A. Jantsch) http://ces.itec.kit.edu J. Henkel, M. Shafique, KIT, WS1011

18 ESII: Specification & Modeling Sorting defined as a relation (src: A. Jantsch) http://ces.itec.kit.edu J. Henkel, M. Shafique, KIT, WS1011

19 ESII: Specification & Modeling Sorting defined as a function (src: A. Jantsch) http://ces.itec.kit.edu J. Henkel, M. Shafique, KIT, WS1011

20 ESII: Specification & Modeling Sorting defined as algorithms (src: A. Jantsch) http://ces.itec.kit.edu J. Henkel, M. Shafique, KIT, WS1011

21 ESII: Specification & Modeling The communication domain (src: A. Jantsch) http://ces.itec.kit.edu J. Henkel, M. Shafique, KIT, WS1011

22 ESII: Specification & Modeling Communication at layout and gate level (src: A. Jantsch) http://ces.itec.kit.edu J. Henkel, M. Shafique, KIT, WS1011

23 ESII: Specification & Modeling Communication between processes (src: A. Jantsch) http://ces.itec.kit.edu J. Henkel, M. Shafique, KIT, WS1011

24 ESII: Specification & Modeling The data domain (src: A. Jantsch) http://ces.itec.kit.edu J. Henkel, M. Shafique, KIT, WS1011

25 ESII: Specification & Modeling The time domain (src: A. Jantsch) http://ces.itec.kit.edu J. Henkel, M. Shafique, KIT, WS1011

26 ESII: Specification & Modeling Notation for abstraction levels computation communication data time (src: A. Jantsch) http://ces.itec.kit.edu J. Henkel, M. Shafique, KIT, WS1011

27 ESII: Specification & Modeling Abstraction levels in design phases (src: A. Jantsch) design phases domains http://ces.itec.kit.edu J. Henkel, M. Shafique, KIT, WS1011

28 ESII: Specification & Modeling Design activities in terms of abstraction levels (src: A. Jantsch) Note: Design activities typically make design decisions and thus refine the design into a model at a lower abstraction level But: analysis activities do not refine models http://ces.itec.kit.edu J. Henkel, M. Shafique, KIT, WS1011

29 ESII: Specification & Modeling Analysis activities in terms of abstraction levels (src: A. Jantsch) Analysis : check for consistency,; produce estimates; - In early design phases -> check for given requirements, for mutual consistency or infer more detailed constraints - May also check feasibility http://ces.itec.kit.edu J. Henkel, M. Shafique, KIT, WS1011

30 ESII: Specification & Modeling The network terminal case study (src: A. Jantsch) CPN: customer premises network http://ces.itec.kit.edu J. Henkel, M. Shafique, KIT, WS1011

31 ESII: Specification & Modeling The network terminal case study (cont’d) (src: A. Jantsch) - Traffic model: based on Asynchronous Transfer Mode (ATM) - ATM: virtual channels can share the same physical transport Medium (like fiber) - ATM switch routes data packets from different virtual channels in the access network to the respective CPN interface and vice versa http://ces.itec.kit.edu J. Henkel, M. Shafique, KIT, WS1011

32 ESII: Specification & Modeling The NT design flow (src: A. Jantsch) http://ces.itec.kit.edu J. Henkel, M. Shafique, KIT, WS1011

33 ESII: Specification & Modeling Models in the NT design (src: A. Jantsch) http://ces.itec.kit.edu J. Henkel, M. Shafique, KIT, WS1011

34 ESII: Specification & Modeling The network terminal case study (cont’d) (src: A. Jantsch) http://ces.itec.kit.edu J. Henkel, M. Shafique, KIT, WS1011

35 ESII: Specification & Modeling Transformations in the NT design (src: A. Jantsch) http://ces.itec.kit.edu J. Henkel, M. Shafique, KIT, WS1011

36 ESII: Specification & Modeling References and Sources  [Vahid02] F. Vahid, T. Givargis, Embedded System Design, John Wiley&Sons, 2002.  [BLee00] B. Lee, Specification and Design of Reactive Systems, PhD Dissertation, UC Berkeley, Spring 2000.  [A. Jantsch] A. Jantsch , “Modeling Embedded Systems and SoCs”, Morgan Kaufmann Publishers, 2004. http://ces.itec.kit.edu J. Henkel, M. Shafique, KIT, WS1011