Decoders and Trees Decoder( n ) n = 1 (base) n > 1 (recursion - PowerPoint PPT Presentation

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Decoder’( n ) n = 1 (base) n > 1 (recursion step) x [0] x [ n − 1] x [ n − 2 : 0] n − 1 Decoder’(n-1) y [1] y [0] 2 n − 1 2 n − 1 2 n − 1 AND (2 n − 1 ) AND (2 n − 1 ) y [2 n − 1 : 2 n − 1 ] y [2 n − 1 − 1 : 0]

Decoder( n ) design shown and proven in class: x R [ k − 1 : 0] � x [ k − 1 : 0] k Decoder( k ) 2 k R [2 k − 1 : 0] 2 n − k × 2 k x L [ n − k − 1 : 0] 2 n − k n − k � Decoder( n − k ) array of x [ n − 1 : k ] AND -gates Q [2 n − k − 1 : 0] R [ r ] Q [ q ] AND q,r y [ q · 2 k + r ]

for k = n-1 : x R [ n − 2 : 0] � x [ n − 2 : 0] n − 1 Decoder( n − 1) 2 n − 1 R [2 n − 1 − 1 : 0] Decoder’( n ) 2 1 × 2 n − 1 x L [0 : 0] 2 1 1 � Decoder(1) array of x [ n − 1] x [ n − 2 : 0] x [ n − 1 : n − 1] AND -gates Q [2 1 − 1 : 0] = Q [1 : 0] n − 1 x [0] Decoder’(n-1) Decoder(1) 2 n − 1 y [1] y [0] 2 n − 1 2 n − 1 AND (2 n − 1 ) AND (2 n − 1 ) y [2 n − 1 : 2 n − 1 ] y [2 n − 1 − 1 : 0]

Decoder’( n ) is a private case of Decoder( n ) design. ( k = n-1 or k = 1 ) Decoder’( n ) is a correct implementation of a decoder. Cost analysis: � � � c INV � if n 1 � � � c n � � � � � � � � n � � � c n c AND c INV 1 � ( 1 ) 2 2 otherwise Solving the recurrence: � � � � � � � � � � � � n � � n c n c n c AND c INV 1 : 1 2 � � � � � � � � � � � � � n � n � � � � � � c c AND n c INV 1 2 � 1 2 2 2 1 � n � 1 2 1 � � � � � � � � n c INV c AND 2 2 � 2 1 � � � � � � � � � n � � � n c INV c AND 1 2 4 asymptotics � � � � n 2

Delay analysis: � � � d INV � if n 1 � d n � ( ) � � � � � � � � � � d INV d n d AND � max , 1 otherwise Solving the recurrence: � � � � � � � � � � � � � � d n d INV d n d AND n max , 1 1 : � � � � � � � d n d AND 1 � � � � � � � � � d n d AND 1 1 � � � � � � � � � d INV n d AND 1 � � � � n Linear Delay!!!

Decoder( n ) for k = n/2 x [ n − 1 : n/ 2] x [ n/ 2 − 1 : 0] Decoder(n/2) Decoder(n/2) B [2 n/ 2 − 1 : 0] A [2 n/ 2 − 1 : 0] B [ ⌊ i/ 2 n/ 2 ⌋ ] A [ i mod 2 n/ 2 ] AND ( i ∈ { 0 , 1 , . . ., 2 n − 1 } ) Y [ i ] � � � � � � � � � � � � I x n n 1 1 : 0 1 : 0 n � A i 2 2 � mod , 2 2 � 0 otherwise � � � � � � � � I n x n � � � i � n n 1 1 : 1 : � � � B 2 2 � � � n � � � � � 0 otherwise 2 2

Consider the top two recursion steps: each AND-gate in the “AND-gates array” of the second recursion step, i.e. Decoder( n/2 ), feeds 2 n/2 AND-gates in the “AND-gates array” of the primary recursion step, i.e. Decoder( n ). n � Maximum fanout of a net 2 2 � � � � � c INV � if n 1 � � n � � 2 � c n � � � � � � � n � c c AND n � 2 2 otherwise 2 � � � d INV � if n 1 � � � d n � � n � ( ) log � � � � � d d AND n � otherwise 2

Design Decoder(n) Decoder’(n) n k=n/2 1 1 1 Cost 2 10 10 4 52 60 8 616 1024 16 132304 262152 Design Decoder(n) Decoder’(n) n k=n/2 1 1 1 � � 2 Delay � � 4 8 7 15 16 9 31

Balanced Trees � � 0 if n 1 � � � d n OR � � � � � � d d OR n � otherwise 2 OR-Tree( n/2 ) OR-Tree( n/2 ) � � � � � � � � d n n d OR log n n 2 2 2 Logarithmic Delay Lower Bound Theorem: Let C = < G , N > denote a combinational circuit that implements a non-constant Boolean function f : {0,1} n � {0,1}. If the fan-in of every gate in G is at most c, then the delay of C is at least log c |cone( f )|. cone(OR n ) = n Delay of the balanced delay(OR n ) � log 2 ( n )·d(OR) tree is minimized. fan-in � 2

Recursive algorithm for computing an OR-tree( n ) 1. The case that n � 2 is trivial. 2. If n > 2, then let a , b be any pair of positive integers such that (i) n = a + b and (ii) max{ � log 2 a � , � log 2 b � } � � log 2 n � - 1. 3. Compute an OR-tree( a ) and an OR-tree( b ). Connect their outputs to an OR-gate to obtain an OR-tree( n ). Claim: the above algorithm computes a minimum delay OR-tree.

Proof: We first show that for every n > 2 there exist a pair of positive numbers a , b such that: � � a b n (i) � � � � � a � � b � � n � 1 (ii) max log , log log 2 2 2 n � � � k � � k a b n 1 there exists one such pair : 2 if 2 2 � � � � � a � � b � � n � 1 obviously, max log , log log 2 2 2 � � k k 1 1 � � � k n � k � a � � � k k 1 a if 2 2 log set : 2 2 � � 2 � k k � b � � � k b n log 2 Note that this is the most 2 unbalanced partition of n, and � k � � n � log 2 1 still we get the minimal delay.

We prove by induction on n that the delay of the computed OR-tree is � log 2 n � ·d(OR) to obtain delay minimality. n = 1 or n = 2 are trivial cases. Induction basis: � � � � � � � � � � � k n d OR tree k k d OR � � Induction hypothesis: . log 2 Induction step: we prove the claim for n , � � � � � � � � � � � � � � � � � � � � � d OR tree n d OR tree a d OR tree b d OR max , � � � � � � � induction hypothesis � � � � a � � b � d OR d OR max log , log 2 2 � � � � � � � � � � � n � d OR d OR log 2 1 � � � n � � � d OR log 2

Buffers � � � buffer � c 1 1 � ! buffer 1 � � � buffer � d 1 1 � fanout 2 A balanced tree structure minimizes the delay and cost. The tree is a binary tree due to fan-out limitations. Notice: * The leaves of the tree feed the gate outputs. * The root of the tree is fed by the gate input. * The first branching is free � no need for a “root” gate. � � � � � � � � � � d n � n � d buffer log 2 1 1 � � � � � � � � � � c n n c buffer 2 1

Fanout limitation effect on design � fanout 2 x [ n − 1] x [ n − 2 : 0] Cost analysis: n − 1 � n 1 : Decoder’(n-1) � � � � � c c INV 1 2 n − 1 1-buf-trees � n 1 : � � � � � � � � � � � n � � c n c n c AND c INV 1 2 2 n − 1 2 n − 1 � � � � � � � � � � � n � � c buf tree c buf 1 2 1 2 1 AND (2 n − 1 ) AND (2 n − 1 ) � � � � � � � � � n � � c n c AND c INV 1 2 y [2 n − 1 : 2 n − 1 ] y [2 n − 1 − 1 : 0] � � � � � n � � � c buf 2 3 1

x [ n − 1] x [ n − 2 : 0] Delay analysis: n − 1 � n 1 : Decoder’(n-1) � � � � � d d INV 1 2 n − 1 1-buf-trees � n 1 : � � � � � � � � % � � � n d INV d buf tree 1 1 2 " " � � � � � � � � � � � � � � n d n d buf d buf tree 1 2 n − 1 2 n − 1 � $ max 1 1 2 " " � � AND (2 n − 1 ) AND (2 n − 1 ) � d n 1 � # � � � d AND y [2 n − 1 : 2 n − 1 ] y [2 n − 1 − 1 : 0] � � � � � � � � � � d INV n d buf � % 1 1 " " � � � � � n d buf � $ max 1 " " � � � d n � # 1 � � � d AND

x [ n − 1 : n/ 2] x [ n/ 2 − 1 : 0] Cost analysis: � � � � � � c c INV n 1 1 : Decoder(n/2) Decoder(n/2) � � � � � � � n B [2 n/ 2 − 1 : 0] A [2 n/ 2 − 1 : 0] � � � n � 1 : c n c c AND n 2 2 2 � � � � 1-buf-trees n n � � � � � c buf tree 2 2 1 2 2 2 B [ ⌊ i/ 2 n/ 2 ⌋ ] A [ i mod 2 n/ 2 ] � � � � � � � n � c c AND n 2 2 AND 2 � � � � n n � � 2 1 � � � c buf 2 2 2 1 2 ( i ∈ { 0 , 1 , . . ., 2 n − 1 } ) Y [ i ] Delay analysis: � � � � � � d d INV n 1 1 : � � � � � � � � � � n � n � � � � � d n d d buf tree d AND n 1 : 1 2 2 2 � � � � � � � � � � � � � d d buf d AND n n 1 1 2 2