9.1 Unit 8 Fundamental Digital Building Blocks: Decoders & Multiplexers
9.2 Checkers / Decoders • Recall – AND gates output '1' for only a single combination – OR gates output '0' for only a single combination – Inputs (inverted or non-inverted) determine which combination is checked for – We say that gate is "checking for" or "decoding" a specific combination X Y Z F X Y Z F 0 0 0 1 0 0 0 0 0 0 1 1 0 0 1 0 0 1 0 1 x 0 1 0 1 x F y F y 0 1 1 1 z 0 1 1 0 z 1 0 0 1 1 0 0 0 1 0 1 1 1 0 1 0 1 1 0 0 AND gate decoding OR gate decoding 1 1 0 0 (checking for) (checking for) 1 1 1 1 combination 010 1 1 1 0 combination 110
9.3 Motivation • Just like there are patterns and structures that occur commonly in nature, there are several common logic structures that occur over and over again in digital circuits – Decoders, Muxes, Adders, Registers • In addition, we design hardware using a hierarchical approach – We design a small component using basic logic gates (e.g. a 1-bit mux) – We build a large component by interconnecting many copies of the small component + a few extra gates (e.g. a 32-bit mux) – We build chips by interconnecting many large components (e.g. a router) – Each components is truly made out of many gates but we the design process is faster and easier by using hierarchy • Let's look at a few common components – We'll start by describing the behavior of the component and then determine what gates are inside
9.4 DECODERS
9.5 Decoders • A decoder is a building block that: – Takes in an n-bit binary number as input – Decodes that binary number and activates the corresponding output – Individual outputs for _____________ input combinations There are gates inside to implement each 3-to-8 Decoder output D0 D1 D2 1 output for each Z (LSB) 3-bit binary D3 combination of the Y number D4 input number X (MSB) D5 D6 D7
9.6 Decoders • A decoder is a building block that: X Y Z D D D D D D D D 0 1 2 3 4 5 6 7 – Takes a binary number as input 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 – Decodes that binary number and activates 0 1 0 0 0 1 0 0 0 0 0 the corresponding output 0 1 1 0 0 0 1 0 0 0 0 – Put in 6=110, Output 6 activates (‘1’) 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 – Put in 5=101, Output 5 activates (‘1’) 1 1 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1 0 0 Binary #6 D0 0 0 D1 0 0 D2 0 1 Z (LSB) 0 0 D3 1 0 Y Only that 0 0 D4 1 1 numbered output is X (MSB) 1 0 D5 activated 0 1 D6 Binary #5 0 0 D7
9.7 Decoder Sizes • A decoder w/ an n-bit input has 2 n outputs – 1 output for every combination of the n-bit input 1 Y0 0 Y1 Y2 0 0 A0 0 D0 0 0 Y Y3 0 0 D1 A1 Y4 0 1 0 D2 (MSB) A2 1 (MSB) X 0 0 D3 Y5 Y6 0 2 n outputs n inputs 0 Y7 (2) (4) 2 n outputs n inputs (3) (8) 2-to-4 3-to-8 Decoder Decoder
9.8 Exercise • Complete the design of a 2-to-4 decoder X Y D0 D1 D2 D3 D0 0 0 Y D1 0 1 D2 (MSB) X D3 1 0 1 1 D0 y D1 D2 x D3
9.9 Building Decoders O0 Checker O0 for 000 A0 O1 Checker O1 for 001 O2 Checker O2 for 010 A1 O3 Checker O3 for 011 3-bit O4 Checker O4 number A2 for 100 [A2:A0] O5 Checker O5 for 101 Checker O6 O6 for 110 Checker O7 O7 for 111
9.10 Vending Machine Example Assuming the keypad produces a 4-bit numeric output, add logic to produce the release signals for each of the 16 vending items. 1 2 3 0 1 2 3 4 5 6 7 8 9 4 5 6 7 0 8 9 10 11 12 13 14 15 Consider any problems with this design.
9.11 Enables • In a normal decoder exactly one output is active at all times • It may be undesirable to always have an active output • We can add an extra input (called an enable) that can independently force all the outputs to their inactive values 0 D0 D0 1 Y Y One output 1 D1 D1 will always 0 D2 D2 0 (MSB) (MSB) X be active X 0 D3 D3 E 2-to-4 Decoder Enable Will force all outputs to 0 when E = 0 (i.e. not enabled)
9.12 Enables 0 D0 1 Y 0 When E=0, Since E=0, D1 inputs is all outputs = 0 0 D2 0 (MSB) X ignored 0 D3 E 0 Enable 0 D0 When E=1, 1 Y 1 inputs will cause the Since E=1, D1 appropriate output to outputs will 0 D2 0 (MSB) X go active function normally 0 D3 E 1 Enable
9.13 Implementing Enables • Original 2-to-4 decoder A ’ B ’ A B D0 A D1 D2 (MSB) B D3 E When E=0, force all outputs = 0 When E=1, outputs operate as they did originally
9.14 Multiplexers • Multiplexers are one of the most common digital circuits • Anatomy: n data inputs, log 2 n select bits, 1 output • A multiplexer (“mux” for short) selects one data input and passes it to the output 4-to-1 Mux S 1 S 0 Y 0 0 i0 i0 0 1 i1 i1 y 1 0 i2 n data inputs 1 output i2 1 1 I3 i3 s log 2 n select bits
9.15 Multiplexers 4-to-1 Mux i0 A i1 B y C 2 Thus, input 2 = C is i2 C S 1 S 0 Y selected and passed i3 D to the output 0 0 i0 s 0 1 i1 1 1 0 i2 Select bits = 10 2 = 2 10 . 1 1 I3 As long as the select bits are 10 2 = 2, whatever bit value appears on input 2 is copied to the output, same as if we had just wired input 2 directly to the output.
9.16 Multiplexers 4-to-1 Mux i0 A i1 B y A 2 Thus, input 0 = A is i2 C S 1 S 0 Y selected and passed i3 D to the output 0 0 i0 s 0 1 i1 1 1 0 i2 Select bits = 00 2 = 0 10 . 1 1 I3
9.17 Exercise: Build a 4-to-1 mux I 0 • Complete the 4-to-1 I 1 mux to the right by Y I 2 drawing wires between the 2-to-4 I 3 decode and the AND S 1 S 0 =00 gates AND Gates acting as barrier gates S 1 S 0 =01 S 1 S 0 =10 Final OR gate takes 3 zero s and one selected input S 1 S 0 =11 2-to-4 Decoder S 1 S 0
9.18 Building a Mux • To build a mux – Decode the select bits and include the corresponding data input. – Finally OR all the first level outputs together. S 1 S 0 Y 0 I 0 0 0 i0 1 S 0 S 1 0 1 i1 0 1 0 i2 I 1 I 1 I 1 1 1 i3 S 0 1 1 S 1 S 1 S 0 = 01 2 1 0 I 1 Y 0 I 2 S 0 1 S 1 0 0 I 3 S 0 1 S 1 0
9.19 Building a Mux • To build a mux – Decode the select bits and include the corresponding data input. – Finally OR all the first level outputs together. S 1 S 0 Y 0 I 0 0 0 i0 1 S 0 S 1 0 1 i1 1 1 0 i2 0 I 1 1 1 i3 S 0 1 S 1 S 1 S 0 = 11 2 1 I 3 Y 0 I 2 S 0 1 S 1 1 I 3 I 3 I 3 S 0 1 1 S 1 1 1
9.20 2-to-1 Multiplexers • We can have design and build muxes with any number of inputs (2-to-1, 5-to-1, 16-to-1, etc.) 2-to-1 Mux i0 A y B 2 Thus, input 1 = B is S Y selected and passed i1 B to the output 0 i0 s 1 I1 1 Select bits = 1 2 = 1 10 .
9.21 Building a 2-to-1 Mux • To build a mux – Decode the select bits and include the corresponding data input. – Finally OR all the first level outputs together. 0 1 1 0 I1 I0 1 0 1 0
9.22 Recall Using T1/T2 1 st Level of AND gates act as barriers only passing 1 channel • • OR gates combines 3 streams of 0’s with the 1 channel that got passed (i.e. ICH1) 2 nd Level of AND gates passes the channel to only the selected output • Connection Essentially this logic ICH1 ICH 0 Point 0 0 forms a 4-to-1 mux OCH 0 where one level of 0 0 gates blocks all but 1 ICH1 ICH1 and then the OR gate ICH 1 0 combines all signals OCH 1 ICH1 1 0 ICH 2 ICH1 0 0 OCH 2 0 0 ICH 3 ICH1 ICH1 0 OCH 3 0 1 0 1 0 0 0 0 0 1 AND: OSEL0 OSEL1 OSEL2 OSEL3 ISEL0 I SEL1 ISEL2 I SEL3 1 AND ICH1 = ICH1 0 AND ICH1 = 0 S0 2-to-4 Decoder S1
9.23 Building Large Muxes • When we build large muxes, the number of inputs to the gates grows too large to build them directly • Instead, we will build larger muxes from smaller muxes • Similar to a tournament of sports teams – Many teams enter and then are narrowed down to 1 winner – In each round winners play _________ Final output Stage 3 Stage 2 Stage 1 Railroad Switch Station
9.24 Design an 8-to-1 mux with 2-to-1 Muxes I0 I 0 Y I1 I 1 S I 0 S0 Y I 1 S I2 I 0 S1 Y I3 I 1 S I 0 S0 Y Y I 1 S I4 I 0 S2 Y I5 I 1 S I 0 S0 Y I 1 S I6 I 0 S1 Y I7 I 1 S S0 S0 S1 S2
9.25 Cascading Muxes • Use several small muxes to build large ones • Rules 1. Arrange the muxes in stages (based on necessary number of inputs in 1 st stage) 2. Outputs of one stage feed to inputs of the next until only 1 final output 3. All muxes in a stage connect to the same group of select bits – Usually, LSB connects to first stage – MSB connect to last stage
9.26 Building a 4-to-1 Mux Stage 1 Stage 2 Rule 1: Outputs from stage 1 D 0 connect to inputs of stage 2 I 0 Y D 1 I 1 S I 0 Y Y S 0 I 1 S D 2 I 0 S 1 Y D 3 I 1 S S 0 Rule 2: LSB S 0 connect to all muxes in first stage. MSB S 1 connects to all 4-to-1 mux built S 0 S 1 muxes in second stage w/ 2-to-1 muxes
9.27 Building a 4-to-1 Mux Stage 1 Stage 2 D 0 I 0 S 1 S 0 Y Y 0 0 D 0 D 1 I 1 S 0 1 D 1 I 0 Y 1 0 D 2 Y S 0 I 1 1 1 D 3 S D 2 I 0 S 1 Y Walk through an D 3 I 1 S example: S 0 S 1 S 0 = 01 S 0 S 1 1 0
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