Data Concentrator SVD data multiplexer with FPGA-based tracking Tracking-Meeting Bayrischzell Jochen Dingfelder, Carlos Mariñas, Michael Schnell schnell@physik.uni-bonn.de University of Bonn July, 19th 2012 Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 1 / 21
Content Motivation 1 Hardware Status 2 FPGA-based tracking 3 Simulation 4 Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 2 / 21
Motivation Motivation optical links Copper ROI Data System Concentrator Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 3 / 21
Hardware Status Content Motivation 1 Hardware Status 2 FPGA-based tracking 3 Simulation 4 Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 4 / 21
Hardware Status Hardware Solution • Advanced Mezzanine Card (AMC) • Redesign with 4 SFP connectors (Zhen-An) → 11 cards • Received during DEPFET meeting in Seeon • Given back to Zhen-An for fixing backplane problems • Start testing, when it returns Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 5 / 21
Hardware Status Simplified Block Diagram AMC "Datcon" AMC "Collector" FD GPU Farm ATCA FD 4:1 Framer FD Mux FD GPU Protocol Framer FD Amplitude FD Ethernet Analysis Frame Collection FD 4:1 Framer FD Mux FD Decoder FD 11:1 Mux FD Track Scheduler & FD reconstruction MMU 4:1 Framer FD Mux FD . FD . 4 GB DDR 2 Memory . Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 6 / 21
FPGA-based tracking Content Motivation 1 Hardware Status 2 FPGA-based tracking 3 Simulation 4 Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 7 / 21
FPGA-based tracking Data Flow Diagram Plan General tracking module interconnection (can also be distributed) Conformal transformation Coordinate Hough SVD strip-data translator transformation ROI Track Intercept creator creation finder ATCA Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 8 / 21
FPGA-based tracking Coordinate Translation LUT for basic location lookup of each ladder With strip ID, strip pitch in u-v direction and DSP of FPGA determine precise position Start Alignment constant for each ladder in u-v direction Constant for sagging correction with LUT of a x 2 function Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 9 / 21
FPGA-based tracking SVD Clustering idea + Take center and size of cluster, saves space and resources − Additional type of data needed Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 10 / 21
FPGA-based tracking General Testing Platform Userland track generation and strip ID calculation Kernel transmission to PCIe over DMA map PCIe 1x transmission to FPGA and init processing FPGA processing and back transmission Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 11 / 21
Simulation Content Motivation 1 Hardware Status 2 FPGA-based tracking 3 Simulation 4 Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 12 / 21
Simulation Real 2D Hit 500 Background hits ( ∼ 1 percent occupancy) 5 generated tracks 0.2 0.15 0.1 0.05 0 y -0.05 -0.1 -0.15 -0.2 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 x Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 13 / 21
Simulation Hough Space Corresponding Hough Space: 30 20 10 0 d -10 -20 -30 -1.5 -1 -0.5 0 0.5 1 1.5 φ Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 14 / 21
Simulation FHT Example With Less Background 30 background hits and 2 tracks in Hough space 30 20 10 d 0 -10 -20 -30 -1.5 -1 -0.5 0 0.5 1 1.5 φ Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 15 / 21
Simulation FHT Example With Less Background 30 background hits and 2 tracks in Hough space with intercept regions 30 20 10 d 0 -10 -20 -30 -1.5 -1 -0.5 0 0.5 1 1.5 φ Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 15 / 21
Simulation FHT Example With Less Background Zoom to one of the intercept regions -1.05 -1.1 -1.15 d -1.2 -1.25 -1.3 -1.35 -1.28 -1.278 -1.276 -1.274 -1.272 -1.27 -1.268 φ Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 15 / 21
Simulation Definitions A few later used definitions: Efficiency: ǫ := number of correct found tracks ǫ ∈ [ 0 , 1 ] total number of real tracks → For all later shown plots: ǫ = 1!! Purity: number of found tracks p := p ≥ 0 total number of real tracks → p ≥ 1 Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 16 / 21
Simulation Track Purity With FPGA Algorithm Simulation 2 1 generated Track 2 generated Tracks 3 generated Tracks 4 generated Tracks # reconstructed tracks / # generated tracks 1.8 5 generated Tracks 1.6 1.4 1.2 1 0.8 100 150 200 300 400 500 Background Hits Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 17 / 21
Simulation Execution Time Running on Core i7 2600 @ 3.8 GHz (with fixed affinity + turbo boost): 5 Create 4.5 Hough Trafo Intercept Finder 4 Intercept Finder (Vertex constrained) 3.5 3 Time [s] 2.5 2 1.5 1 0.5 0 100 200 300 400 500 600 700 800 900 1000 Hits Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 18 / 21
Simulation Visualization Software For visualization full VXD (SVD, PXD) with active area and strip and pixel structure Marking background, tracks, clusters... Presentation Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 19 / 21
Simulation Summary and Status 2D Simulation of the SVD (r- ϕ plane only), r-z plane in progress Track reconstruction efficiency is high, but... tracks with Gaussian smearing only (2 strip pitches) No multiple scattering, energy loss, magnetic field inhomogeneities... → Switch to the basf2 framework • Done, but only with local coordinates of sensors. • Hough transformation only feasible with up to 1 − 2 percent occupancy Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 20 / 21
Simulation Thank you for your attention! Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 21 / 21
Backup Technical Specifications Technical Specification on I/O Input: Up to 42 (32) optical-fibre links 1.5 Gbps max On average 110 Mbps expected Dynamic bandwidth Output: 6.25 Gbps over backplane or SFP+ 440 Mbps → Total: 4 . 6 Gbps ≈ 550 MiB/s average data rate Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 21 / 21
Backup Idea Tracking Options 4 3.5 Hough Transformation to find 3 2.5 straight and arc tracks (after y 2 1.5 conformal transformation) 1 0.5 0 Can be fast and efficient 0 0.5 1 1.5 2 2.5 3 3.5 4 x implemented in the FPGA over Hough Fast Hough Transformation (FHT) transformation 1 First 2D resulsts of the next slides 0.5 Open for other algorithm, like 0 a sector-neighbour finding cellular -0.5 automaton or Kalman-Filter -1 0 0.5 1 1.5 2 m Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 21 / 21
Backup FPGA Implementation Trigonometric Functions and Memory Requirements Need trigonometric functions like sine and cosine e.g. for coordinate transformation CORDIC: Basic Lookup table for nodes and a shift-add implementation of approximation function Pure LUT: Large Lookup table for every value (high memory requirements) FPGAs’ DSPs used as Multiplier/Divider unit. Block Memory needed to translate strip IDs into coordinates and ROI creation Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 21 / 21
Backup FPGA Implementation Status of the Different Blocks in Simulations AMC "Datcon" AMC "Collector" FD GPU Farm ATCA FD 4:1 Framer FD Mux FD GPU Protocol Framer FD Amplitude FD Ethernet Analysis Frame Collection FD 4:1 Framer FD Mux FD Decoder FD 11:1 Mux FD Track Scheduler & FD reconstruction MMU 4:1 Framer FD Mux FD . FD . 4 GB DDR 2 Memory . Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 21 / 21
Backup Multiplexer Theory Multiplexing Three general types of multiplexing: Frequency Division Multiplexing (FDM) Time Division Multiplexing (TDM) Statistical Multiplexing Because of dynamic bandwidth “Statistical Multiplexing” would be most suitable Demultiplexing is trivial, if only multiplexing of 32 bit words is ensured Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 21 / 21
Backup Multiplexer Theory Aurora overview Xilinx Aurora protocol as physical link layer over GTP Takes care of every “low level” operation like clock correction, symbol decoding and 8B/10B Encoding Easy data transmission/framing over locallink Error detection and initialization Status wires for channel and lanes Lane: One communication line Channel: Concentration of one or more lanes Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 21 / 21
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