CSH Consulting, LLC Signal Integrity Consulting April 2020 - PowerPoint PPT Presentation

CSH Consulting, LLC Signal Integrity Consulting April 2020 www.cshconsulting.net chris.heard100@gmail.com. 603-494-9277

Overview • High Speed Serial Channel Modeling – 25Gbps Ethernet, 56G PAM-4, PCIe GenX, Fibre Channel, SAS, USB – Anything over 2Gb/s requiring frequency domain simulation and modeling. • High Speed Memory Simulation – DDR2, DDR3, DDR4 – Clock, Address, Data, Strobe – Buffer Strengths, On Die Termination, Topology, Waveform Integrity, Setup and Hold Mask Evaluations for DQ and Command/Control/Address. – DQ Rx Eye Mask for DDR4 • Power Integrity Simulation – DC Analysis and Frequency Response Analysis of Power Planes – Decoupling Capacitor Optimization • CAD Guidelines – Concise recommendations for PCB Layout based on Pre-Layout Simulations.

Simulation Capability • Software Resources –Ansys HFSS •3D Modeling of structures (vias, AC Caps, BGAs, Connectors) •3D Modeling of pcb etch. •In-house automation ensures faster response and consistency –Ansys SIwave •Power Plane Voltage Drop simulation •Power Plane Frequency analysis and decoupling capacitor optimization –Keysight ADS • Statistical Eye simulation using IBIS-AMI Models –HSpice •Time Domain Simulation using IBIS •Frequency Domain Simulation – Concatenation of S-Parameters

Channel Modeling - Process and Tools BGA Transition PCB Connector Connector BGA Via Connector Package Via Etch Footprint Footprint Backplane Etch BGA PCB PCB Connector Connector AC Cap Connector Package Etch Etch Footprint Footprint • Link Models created in HSpice –Cascaded S-parameters of connector, footprint, etch • Connector Models –Provided by Connector Vendor in Touchstone format. • PCB Footprints –Simulated in Ansoft HFSS • Each one is different! • PCB Etch Models –Tabular W-element RLGC Models generated in Apsim RLGC. –De-Embedded S-parameter Model generated in HFSS

Passive Channel Design Drivers • Insertion Loss – Driven by PCB material property and via stubs. • Return Loss – Driven by Impedance mismatches mainly arising in component footprints. • Crosstalk – Unwanted electromagnetic coupling between traces, vias and connector contacts. • Skew – Driven by routing, connector, and PCB laminate material. • Common Mode Conversion and EMI – Driven by unbalanced differential pairs in routing and connectors.

PCB Material Property Extraction From Measurements

Insertion Loss vs PCB and Cable Material Loss Characteristic of 1m of Copper Medium 0 -5 -10 -15 High Confidence Region -20 (< 30dB) -25 -30 Magnitude (dB) -35 Near Limit ( 30-40dB) -40 No Operation -45 -50 -55 -60 -65 26AWG EXD Length: 1m -70 Megtron-7NE RA Line Width: 6.5mil Megtron-7NE Line Space: 8.5mil -75 Copper Weight: ½ oz Megtron-6 FlatBond -80 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 Frequency (GHz)

Insertion Loss vs. Line Width Megtron 6 Insertion Loss: 40 inches 0 -2 sdd12-5p5 -4 sdd12-6p5 -6 -8 -10 -12 -14 Magnitude (dB) -16 -18 -20 -22 -24 -26 -28 -30 -32 -34 -36 -38 -40 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Frequency (GHz)

Crosstalk Sources 3h-5h h 1. Between Differential Pair Traces – Crosstalk Target < = -50dB 2. Between Vias in Footprint – Simulate and Tune • Antipad shapes • Drill size • Pad Size • Backdrill Depth 3. Within Connectors FEX T Contributors (GH2 Driven) 0 -10 – Simulate and tune conductor geometry, -20 -30 plastic materials and return paths. -40 -50 -60 -70 -80 -90 -100 0 2 4 6 8 10 Frequency (Hz) 9 x 10

DC Blocking Capacitor Example 85 0 20 65 0 20 Cap 0402 Clearance Layer 2 154 174 Diff Port Zo 100 Finished Dia 5.8mil Layer Escape 8 Material Megtron-4 Drill Dia 9.8mil Line Width 4.25mil Dk 3.8 Pad Dia 20.0mil EtchBack 0.1mil Df 0.01 Antipad Dia 51.0mil Line Space 11.5mil Layers 10 Max Freq. 20 GHz Oval Dogbone 51.0mil Anti Line Width 4.25mil Thickness 61.4 mil Adapt Freq. 10 GHz

DC Blocking Capacitor Example Results Insertion Loss, Return Loss and TDR Differential Insertion and Return Loss: Riser ACCap L8 TDR: Riser-ACCap-L8 0 105 -5 92.6 to 104.8 ohms -10 100 -28.5dB @ 5.0GHz -15 Magnitude (dB) Ohms -20 95 -25 -30 90 Sdd12 -35 Sdd11 Goal Riser-ACCap-L8 -40 85 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 0 0.1 0.2 0.3 0.4 Frequency (GHz) Time (nS)

IEEE 802.3ap KR (10Gbps): Insertion Loss and ILD Channel Example 0 5 4 -10 3 -7.6dB @ 5.0GHz Range: 1.28 dB -20 2 1 Magnitude (dB) Magnitude (dB) -30 0 -40 -1 -2 -50 -3 Simulated Link-Sdd65 -60 Simulated Link LS IL Deviation Simulated-Sdd65 -4 IL Mask High IL Deviation High IL Mask Low IL Deviation Low -70 -5 0 2 4 6 8 10 1 2 3 4 5 6 Frequency (GHz) Frequency (GHz)

IEEE 802.3ap KR (10Gbps): Return Loss and ICR Channel Example ICR Pinout 1: Intel KR Riser to Denali 1p0 Channel Rx 0 80 Simulated Link-Sdd11 Next2x1, Next3x1, Fext1x1 Return Loss Mask -5 70 37.3dB @ 5.0GHz -12.2dB @ 5.0GHz -10 60 -15 50 Magnitude (dB) Magnitude (dB) -20 40 -25 30 -30 20 Simulated Link -35 10 Simulated Link LS ICR Mask -40 0 -1 0 1 -1 0 10 10 10 10 10 Frequency (GHz) Frequency (GHz)

IEEE 802.3bj (25Gbps) Insertion and Return Loss Channel Example 0 0 -15.4dB @ 12.5GHz -20.1dB @ 12.5GHz -10 -5 -20 -10 -30 -15 Magnitude (dB) Magnitude (dB) -40 -20 -50 -25 -60 -30 -70 -35 Simulated Link Simulated Link IL Mask RL Mask -80 -40 0 5 10 15 20 25 0 5 10 15 20 25 Frequency (GHz) Frequency (GHz) sdd12=s16ptest.sdd(:,2,1); sdd11=s16ptest.sdd(:,2,2);

IEEE 802.3bj (25Gbps) Crosstalk and ICR Channel Example Insertion Loss and Crosstalk: Lepton 25G Examax Post Layout Channel 0 0 Fext1x1, Fext2x1, Fext3x1 Fext1= 6,1. Fext2= 6,3. Fext3= 6,7. -5 -10 39.0dB @ 12.5GHz -10 -20 -15 -20 -30 -25 -40 Magnitude (dB) Magnitude (dB) -30 -50 -35 -40 -60 -45 -70 -50 -55 -80 -60 Fext1 -90 Sdd65 Fext2 -65 Fext3 TotalXTK:RMS -100 -70 0 5 10 15 20 25 30 35 40 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 Frequency (GHz) Frequency (GHz)

Channel TDR Channel Example 110 105 100 95 Ohms 90 85 80 Lepton 25G Examax Post Layout Channel 75 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Time (nS)

SIwave: Power Plane Voltage Drop

SIwave: Power Plane Impedance vs. Frequency Power Plane Impedance at U2. File: ..\Plane_Only_SYZ.xls 1000 100 10 Impedance (ohms) 1 Goal: 0.080ohm @ 40.0MHz. 0.1 0.01 Plane Only Plane With Caps Goal 0.001 0.1 1 10 100 1000 Frequency (MHz)

ADS Schematic: 1 Million Bit-By-Bit Simulation

Statistical Eye: 25Gbps 1 Million Bit-By-Bit Simulation

Statistical Eye: 6.25Gbps Measurement vs. Simulation Measurement 240mV 0.76UI 162mV 0.70UI Simulation (from LinkEye)

600MHz DDR4 Post-Layout Address Path Micron MT40A512M16LY Ibis model: z11b.ibs TLB Package: z11b_96ball_pkg Width Layer Zo 0.60V Input Model: INPUT 4.25 mil 14 40 Xilinx 30Ω U114 U111 U110 U112 U113 U2 TLB: Extracted TLB: Extracted TLB: Extracted TLB: Extracted TLA: Extracted TLA: Extracted Model: HP_SSTL12_DCI_M_OUT40 Corner: Slow-Slow MT40A512M16JY Package: xczu7eg_ffvc1156 1200MHz, 2400 AC100 Vref = 0.600V VIHAC 700 VIHDC 675 VREF 600 VILDC 525 VILAC 500 tIS 55+ tIH 80+

Clock and Address Extracted Nets Nets to Extract: DDR_CK0_N DDR_CK0_P DDR_PARITY DDR_ADD(11) DDR_ADD(2) DDR_ADD(8) DDR_ADD(0) DDR_ADD(6) DDR_ADD(4) DDR_BA0 DDR_ADD(10) DDR_BG0 DDR_ACT_L DDR_WE_L DDR_ODT0 DDR_CKE0 GND