λ CS 251 Fall 2019 CS 240 Spring 2020 Principles of Programming Languages Foundations of Computer Systems Ben Wood Ben Wood Virtual Memory Process Abstraction, Part 2: Private Address Space Motivation : why not direct physical memory access? Address translation with pages Optimizing translation : translation lookaside buffer Extra benefits : sharing and protection Memory as a contiguous array of bytes is a lie! Why? https://cs.wellesley.edu/~cs240/s20/ Virtual Memory 1
Problems with physical addressing Main memory 0: 1: 2: Physical address 3: (PA) CPU 4: 4 5: 6: 7: 8: ... M-1: Data Virtual Memory 2
Problem 1: memory management Main memory Process 1 stack × Process 2 heap What goes Process 3 where? code … globals Process n … Also: Context switches must swap out entire memory contents. Isn't that expensive ? Virtual Memory 3
Problem 2: capacity 64-bit addresses can address Physical main memory offers several exabytes a few gigabytes (18,446,744,073,709,551,616 bytes) (e.g. 8,589,934,592 bytes) ? (To scale with 64-bit address space, you can't see it.) 1 virtual address space per process, with many processes… Virtual Memory 4
Problem 3: protection Physical main memory Process i Process j Problem 4: sharing Physical main memory Process i Process j Virtual Memory 5
Solution: Virtual Memory (address indirection ) data Virtual address space Process 1 virtual Physical memory addresses virtual-to-physical mapping physical Virtual address space addresses Process n virtual addresses data Single physical address space Private virtual address space per process. managed by OS/hardware. Virtual Memory 6
Indirection "2" (it's everywhere!) 0 1 Direct naming "2" Thing 2 "2" 3 What X 4 currently "x" maps to 5 Indirect naming 2 6 "x" "x" 7 "x" What if we move Thing ? Virtual Memory 7
Tangent: i ndirection everywhere • Pointers • Constants • Procedural abstraction • Domain Name Service (DNS) • Dynamic Host Configuration Protocol (DHCP) • Phone numbers • 911 • Call centers • Snail mail forwarding “Any problem in computer science can be solved by adding another level of indirection.” • … –David Wheeler, inventor of the subroutine, or Butler Lampson Another Wheeler quote? "Compatibility means deliberately repeating other people's mistakes." Virtual Memory 8
Virtual addressing and address translation Memory Management Unit translates virtual address to physical address Main memory 0: CPU Chip 1: 2: Virtual address Physical address 3: (VA) (PA) CPU MMU 4: 4 4100 5: 6: 7: 8: ... M-1: Data Physical addresses are invisible to programs. Virtual Memory 9
Page-based mapping fixed-size, aligned pages page size = power of two Virtual Address Space 0 Virtual Physical Page Address Space 0 0 Physical Virtual Page Page 0 1 Physical Virtual Page Page 1 2 … Virtual Map virtual pages Page … 3 onto physical pages. Physical Page 2 p - 1 2 m - 1 Virtual Page 2 v - 1 2 n - 1 Some virtual pages do not fit! Where are they stored? Virtual Memory 10
Cannot fit all virtual pages! Where are the rest stored? Virtual Memory virtual address space Address Space usually much larger than 0 physical address space Virtual Physical Memory Page Address Space 0 0 Physical Virtual Page Page 0 1 Physical Virtual Page Page 1 2 … Virtual Page … 3 1. On disk if used Physical Page 2 p - 1 2 m - 1 Virtual Page 2 v - 1 2. Nowhere if not (yet?) used 2 n - 1 Virtual Memory 11
Not drawn to scale Virtual memory: cache for disk? SRAM DRAM ~4 MB ~8 GB ~500 GB L1 I-cache L2 Disk Main unified 32 KB Memory cache L1 CPU Reg D-cache Throughput: 16 B/cycle 8 B/cycle 2 B/cycle 1 B/30 cycles solid-state "flash" Latency: 3 cycles 14 cycles 100 cycles millions or spinning magnetic platter. Cache miss penalty (latency): 33x Memory miss penalty (latency): 10,000x Example system Virtual Memory 12
Design for a slow disk: exploit locality Virtual Memory Address Space 0 Virtual Physical Memory Page Address Space 0 0 Physical Virtual Page Page 0 1 Physical Virtual Page Page 1 2 … Virtual Page … 3 on disk Physical Page 2 p - 1 2 m - 1 Virtual Page 2 v - 1 2 n - 1 Virtual Memory 13
Design for a slow disk: exploit locality Virtual Memory Large page size Page size? Address Space usually 4KB, up to 2-4MB 0 Virtual Physical Memory Page Address Space 0 0 Physical Virtual Page Page Fully associative 0 1 Associativity? Store any virtual page in any physical page Physical • Virtual Page Large mapping function • Page 1 2 … Virtual Page … 3 on disk Physical Page 2 p - 1 2 m - 1 Virtual Sophisticated Replacement Page 2 v - 1 replacement policy policy? 2 n - 1 Write Write-back Not just hardware • policy? Virtual Memory 14
Address translation Main memory 0: CPU Chip 1: 2: Virtual address Physical address 3: (VA) (PA) CPU MMU 4: 4 4100 5: 6: 7: 8: ... M-1: Data Virtual Memory 15
Page table Physical pages array of page table entries (PTEs) (Physical memory) mapping virtual page to where it is stored VP 1 PP 0 Physical Page Number or disk address Valid VP 2 null PTE 0 0 VP 7 1 1 VP 4 PP 3 0 1 null 0 0 PTE 7 1 Swap space page table (Disk) VP 3 Memory resident, VP 6 managed by HW (MMU), OS How many page tables are in the system? Virtual Memory 16
Address translation with a page table Virtual address (VA) Page table base register Virtual page number (VPN) Virtual page offset (VPO) (PTBR) Base address Page table of current process's page table Valid Physical page number (PPN) Virtual page mapped to physical page? yes = page hit Physical page number (PPN) Physical page offset (PPO) Physical addres s (PA) Virtual Memory 17
Page hit: virtual page is in memory Physical pages (Physical memory) Virtual Page Number VP 1 PP 0 Physical Page Number or disk address Valid VP 2 null PTE 0 0 VP 7 1 PP 0 1 PP 1 VP 4 PP 3 0 On disk 1 PP 3 null 0 0 On disk PTE 7 1 PP 2 Swap space page table (Disk) VP 3 VP 6 Virtual Memory 18
Page fault: Physical pages (Physical memory) Virtual Page Number VP 1 PP 0 Physical Page Number or disk address Valid VP 2 PP 1 null PTE 0 0 VP 7 PP 2 1 PP 0 1 PP 1 VP 4 PP 3 0 On disk 1 PP 3 null 0 0 On disk PTE 7 1 PP 2 Swap space page table (Disk) VP 3 VP 6 Virtual Memory 19
Page fault: exceptional control flow Process accessed virtual address in a page that is not in physical memory. Process User Code OS exception handler exception: page fault movl Load page into memory return Returns to faulting instruction: movl is executed again ! Virtual Memory 20
Page fault: 1. page not in memory Physical pages (Physical memory) ! n o Virtual Page Number i t p e c x E VP 1 PP 0 Physical Page Number or disk address Valid VP 2 null PTE 0 0 VP 7 1 PP 0 1 PP 1 VP 4 PP 3 0 On disk 1 PP 3 null 0 0 On disk PTE 7 1 PP 2 Swap space page table (Disk) VP 3 What now? VP 6 OS handles fault Virtual Memory 21
"Page out" Page fault: 2. OS evicts another page. Physical pages (Physical memory) Virtual Page Number VP 1 PP 0 Physical Page Number or disk address Valid VP 2 null PTE 0 0 VP 7 0 On disk 1 PP 1 VP 4 PP 3 0 On disk 1 PP 3 null 0 0 On disk PTE 7 1 PP 2 Swap space page table (Disk) VP 3 VP 6 VP 1 Virtual Memory 22
"Page in" Page fault: 3. OS loads needed page. Physical pages (Physical memory) Virtual Page Number PP 0 VP 3 Physical Page Number or disk address Valid VP 2 null PTE 0 0 VP 7 1 On disk 1 PP 1 VP 4 PP 3 1 PP 0 1 PP 3 null 0 0 On disk PTE 7 1 PP 2 Swap space page table (Disk) VP 3 Finally: VP 6 Re-execute faulting instruction. Page hit! VP 1 Virtual Memory 23
Terminology context switch Switch control between processes on the same CPU. page in Move page of virtual memory from disk to physical memory. page out Move page of virtual memory from physical memory to disk. thrash Total working set size of processes is larger than physical memory. Most time is spent paging in and out instead of doing useful work. Virtual Memory 24
Address translation: page hit 2 CPU Chip PTEA 1 PTE VA Cache/ CPU MMU 3 Memory PA 4 Data 5 1) Processor sends virtual address to MMU ( memory management unit ) 2-3) MMU fetches PTE from page table in cache/memory 4) MMU sends physical address to cache/memory 5) Cache/memory sends data word to processor Virtual Memory 25
Address Translation: Page Fault Exception Page fault handler 4 2 CPU Chip Victim page PTEA 1 5 VA PTE Cache/ CPU MMU Disk Memory 3 7 New page 6 1) Processor sends virtual address to MMU 2-3) MMU fetches PTE from page table in cache/memory 4) Valid bit is zero, so MMU triggers page fault exception 5) Handler identifies victim (and, if dirty, pages it out to disk) 6) Handler pages in new page and updates PTE in memory 7) Handler returns to original process, restarting faulting instruction Virtual Memory 26
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