Cross Link Insertion for Improving Tolerance to Variations in Clock - PowerPoint PPT Presentation

Cross Link Insertion for Improving Tolerance to Variations in Clock Network Synthesis Tarun Mittal Cheng-Kok Koh School of Electrical and Computer Engineering Purdue University

Presentation Flow Introduction  Comparison of link insertion schemes  Clock Network Synthesis  Experimental Results  Conclusions and Future Work 

Insertion of Cross link Current approach to Clock Network Synthesis  Clock Trees  - Shorter Wiring - Unique path from source to sinks - More susceptible to process variations

Insertion of Cross link Current approach to Clock Network Synthesis  Clock Trees  - Shorter Wiring - Unique path from source to sinks - More susceptible to process variations Clock Mesh  - Higher wiring cost - Many paths from source to sinks - More robust to process variations

Insertion of Cross link Current approach to Clock Network Synthesis  Clock Trees  - Shorter Wiring - Unique path from source to sinks - More susceptible to process variations Clock Mesh  - Higher wiring cost - Many paths from source to sinks - More robust to process variations Cross link form a compromise between  clock trees and clock meshes

Effect of cross link insertion Change in skew between source nodes u and v due to cross link addition T q u,v = α q u,v + αβ where q p q u,v =skew after link addition crosslink q u,v =skew before link addition T a v u T i l T j T b

Effect of cross link insertion Change in skew between source nodes u and v due to cross link addition T q u,v = α q u,v + αβ R loop where q p q u,v =skew after link addition q u,v =skew before link addition T a v u α=R l /R loop R l T b

Effect of cross link insertion Change in skew between source nodes u and v due to cross link addition T q u,v = α q u,v + αβ R u,u − R v,v where q q u,v =skew after link addition p q u,v =skew before link addition T a v u α=R l /R loop C l T b β=Cl/2(R u,u -R v,v )

Comparison of Link insertion schemes  Method 1: source p - Link l 1 is inserted between two sinks u and v buf i buf j l i l j - This method of link insertion is l 1 used in [Rajaram-Hu, ISPD'05] r i r j u v T i T j Method 1

Comparison of Link insertion schemes  Method 1: source p - Link l 1 is inserted between two sinks u and v buf i buf j l i l j - This method of link insertion is l 1 used in [Rajaram-Hu, ISPD'05] r i r j u v  Method 2: T i T j Method 1 - Link l 2 is inserted between two higher level internal nodes u and v source p - This method of link insertion is l 2 used in our approach buf i buf j l i l j v u r i v , r j u , T i T j Method 2

Comparison of Link insertion schemes  Method 1: source p - Link l 1 is inserted between two sinks u and v buf i buf j l i l j - This method of link insertion is l 1 used in [Rajaram-Hu, ISPD'05] r i r j u v  Method 2: T i T j Method 1 - Link l 2 is inserted between two higher level internal nodes u and v source p - This method of link insertion is l 2 used in our approach buf i buf j l i l j  l 2 << l 1 satisfies α 2 <α 1 & β 2 <β 1 v u r i v , r j u , T i T j Method 2

Effect of cross link on sink delays

Sinks are in the same subtree source Method 1:  T - m and n have different path lengths to the end point of the q cross link p buf i - skew variability depends upon T a locality of sink node to the end crosslink r i r j point of the cross link T b T i u v m n Method 1

Sinks are in the same subtree source Method 1:  T - m and n have different path lengths to the end point of the q cross link p buf i - skew variability depends upon T a locality of sink node to the end crosslink r i r j point of the cross link T b T i u v m n Method 1 source Method 2:  - m and n have nearly same path T lengths to the end point of cross q link p buf i buf j crosslink - skew variability is same for the T a v u sink nodes l r i r j T b T j T i u' v' m n Method 2

Measured skew variability for both methods Range is 0 . 75ps Range is 0 . 2ps Range is 0 . 4ps Range is 0 . 06ps

Sinks are in different sub-trees connected by the cross link source Method 1:  T - Different delays for sinks within a sub-tree q p - Non uniform correlation between buf i the sink pairs m and n crosslink r i T a r j T b T i m n Method 1

Sinks are in different sub-trees connected by the cross link source Method 1:  T - Different delays for sinks within a sub-tree q p - Non uniform correlation between buf i the sink pairs m and n crosslink r i T a r j T b T i m n Method 1 Method 2:  source - Same delays for sinks within a sub-tree T - Uniform correlation between all q sink pairs m and n p buf i crosslink buf j T a v u l r i r j T b T j T i n m Method 2

Sinks are in two disjoint sub-trees source No predictable correlation  between delays of sinks m and n due to no overlap T path q Both Method 1 and p  Method 2 are equally buf i buf j crosslink ineffective in this T a v u situation. l r i r j T b T j T i n m

Clock Network Synthesis Our clock network synthesis is based on the usage  of Method 2 for cross link insertion. Problem formulation is based on ISPD'10 High  performance Clock Network Synthesis contest. Our approach to clock network synthesis consists of  3 main steps - Merging - Buffer Insertion - Link Insertion

Problem Formulation Given: Sinks, Blockages and clock source location  Objective: Generate a clock network T that  connects clock source to the sinks. Constraints:  - All sink pairs with distance between them less than user specified distance are called local sink pairs. - All local sink pairs should satisfy Local clock skew constraint (LCS). - Slew at any point should be less than predefined limit S. - Buffers should not be placed in the blockages

Merging General framework of Clock network synthesis is  based on the Deferred-Merge embedding approach A = Merge  s 1 ,s 2  s 2 s 1 B = Merge  s 3 ,s 4  s 3 s 0 s 4

Merging General framework of Clock network synthesis is  based on the Deferred-Merge embedding approach A = Merge  s 1 ,s 2  s 2 C = Merge  A, B  s 1 B = Merge  s 3 ,s 4  s 3 s 0 s 4

Merging General framework of Clock network synthesis is  based on the Deferred-Merge embedding approach A = Merge  s 1 ,s 2  s 2 C = Merge  A, B  s 1 B = Merge  s 3 ,s 4  s 3 s 0 s 4

Merging General framework of Clock network synthesis is  based on the Deferred-Merge embedding approach A = Merge  s 1 ,s 2  s 2 C = Merge  A, B  s 1 B = Merge  s 3 ,s 4  s 3 s 0 s 4

Merging In bottom-up phase clock tree is constructed  iteratively. locked testbuffer Slew buf i buf j violation p r i l i l j T i T j r i r j T i T j p No slew r i r j violation T i T j

Buffer Insertion Slew constraints results in  the buffer insertion in clock tree. Buffers are inserted on the  stem wires. mr buf i NGSPICE simulations are used  buf i to compute the length of ms r i stem wire. r i Each buffer buf i has a l i  merging region mr bufi T i associated with it.

Buffer Insertion Slew constraints results in  the buffer insertion in clock tree. blockage Buffers are inserted on the  stem wires. mr buf i NGSPICE simulations are used  buf i to compute the length of ms r i stem wire. r i Each buffer buf i has a l i  merging region mr bufi T i associated with it. Blockage avoidance is  considered

Link Insertion buf i buf j crosslink v l i u l j l v l u l min r i r j T i T j

Link Insertion buf i buf j crosslink l v v Step 1 l i u l min l j ms r j l v l u l min r i r j ms r i l u T i T j

Link Insertion buf i buf j crosslink l v v Step 1 l i u l min l j ms r j l v l u l min r i r j ms r i l u T i T j l v +l min

Link Insertion buf i buf j crosslink l v v Step 1 l i u l min l j ms r j l v l u ms u l min r i r j ms r i ms v l u T i T j l v +l min

Link Insertion buf i buf j crosslink l v v Step 1 l i u l min l j ms r j l v l u ms u l min r i r j ms r i ms v l u T i T j l v +l min l j − l v ms v l i − l u Step 2 ms u buf min

Link Insertion buf i buf j crosslink l v v Step 1 l i u l min l j ms r j l v l u ms u l min r i r j ms r i ms v l u T i T j l v +l min l j − l v ms v l i − l u Step 2 l j − l v +buf min ms u buf min

Link Insertion buf i buf j crosslink l v v Step 1 l i u l min l j ms r j l v l u ms u l min r i r j ms r i ms v l u T i T j l v +l min l j − l v ms v buf j loc l i − l u buf i loc Step 2 l j − l v +buf min ms u buf min

Merits of our design flow Our link insertion flow allows us to control the link ● length. Inserting link below the buffer helps in reducing the ● variation effects of buffer as compared to inserting above it. Cross link maximizes the reduction of the skew ● variability for the sinks in the same sub-tree Cross link improves the correlation of the sink delays ● in the two sub-trees that are connected by the cross link .