CREATING, ACQUIRING AND INTEGRATING REUSABLE IP Prof. Don Bouldin, Ph.D. Electrical & Computer Engineering University of Tennessee Knoxville, TN 37996-2100 dbouldin@tennessee.edu IEEE Boston 14 November 2007 http://vlsi1.engr.utk.edu/~bouldin/boston 1 1
OUTLINE OF THIS PRESENTATION • Design Productivity • Intellectual Property Blocks • Reuse Requirements • The Changing Design Environment • Acquiring IP Blocks • Quality IP Metrics • Collaborative Design 2 2
ELECTRONIC PRODUCTS ARE PERVASIVE AND ALWAYS IMPROVING Moore’s Law: Every 18 months integrated circuit manufacturing can produce Moore’s Law: Every 18 months integrated circuit manufacturing can produce 2X performance for the same price or the same performance for half the price. 2X performance for the same price or the same performance for half the price. $1000--1X $1000--1X Price Price $1000--2X $1000--2X $500--1X $500--1X Performance Performance 3 3
A DESIGN PRODUCTIVITY CRISIS WAS PREDICTED A DECADE AGO The Impending Design Productivity Crisis Logic Transistors per Chip 10,000,000 100,000,000 Logic Tr./Chip 1,000,000 10,000,000 Tr./S.M. Trans./Staff-Mo. 100,000 1,000,000 Productivity 58%/Yr. Compounded Complexity growth rate 10,000 100,000 (K) 1,000 10,000 x 100 1,000 xx 21%/Yr. Compounded x x x Productivity growth rate x 10 100 __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ 1 10 1981 1983 1985 1987 1989 1991 1993 1995 1997 1999 2001 2003 2005 2007 2009 Source: SEMATECH Maya Rubeiz USAF Wright Labs maya.rubeiz@sn.wpafb.af.mil http://rassp.scra.org 1997 4 4
DESIGN PRODUCTIVITY HAS PROGRESSED RECENTLY • 1947 • 2007 • 3 Nobel Laureates • 3 ECE Students • 1 Transistor • 4M Transistors Progress has been enabled by raising the level of abstraction and reusing previous sub-systems or blocks. 5 5
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WE BUILD SKYSCRAPERS USING STANDARDIZED BLOCKS So, let’s use standardized blocks to build systems Sears Tower, Chicago Sears Tower, Chicago www.lego.com www.lego.com 7 7
INTELLECTUAL PROPERTY BLOCKS Design #1 without Design #2 without Design #3 without Planned Reuse Planned Reuse Planned Reuse 1.5 1.8 2.1 Design #2 Design #3 Design # 1 For Reuse WITH IP WITH IP Often, IP are more like patches that must be IP blocks should have well-defined interfaces stitched together like a quilt 8 8
IP IS CREATED USING A HARDWARE DESCRIPTION LANGUAGE OR HDL CASE y IS WHEN A => IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ; WHEN B => IF w = '0' THEN y <= A ; ELSE y <= C ; END IF ; WHEN C => IF w = '0' THEN y <= A ; ELSE y <= C ; END IF ; END CASE ; 9 9
AN HDL DESIGN CAN BE TARGETED TO MULTIPLE LAYOUTS LIBRARIES SYNPLIFY_PRO SYNPLIFY_PRO HDL architecture behavior of control is if left_paddle then SYNTHESIS TECH TECH n_state <= hit_state elsif n_state <= miss_state A B end if; SCHEMATIC--A SCHEMATIC--B TECH AND OR TECH OR OR A AND B AND ALTERA XILINX PLACE & ROUTE PLACE & ROUTE PHYSICAL LAYOUT PHYSICAL LAYOUT 10 10
REQUIREMENTS FOR REUSABLE IP • BASICS: • ALSO NEED: – HDL Models – Test Bench (Input Stimuli/Output – Functional Description Responses – Application Intent – Tools and Versions – Interface Used/Needed Specifications – Foundry Used For Fab – Authors and Owners – Size, Delay, Power – Size, Delay, Power Measurements Estimates – Testability Features – Packaging Info (BIST, JTAG, SCAN) 11 11
THE DESIGN METHOD HAS CHANGED CUSTOMER Requirements UNCHANGED UNCHANGED DESIGNER Specifications OLD METHOD NEW METHOD OLD METHOD NEW METHOD 1. Select ICs 1. Select PCB with ICs 2. Design/Fab PCB 2. Select blocks for new IC 3. Design blocks for new IC 3. Design missing blocks 4. Integrate blocks 4. Integrate blocks 5. System Integration 5. System Integration 12 12
IP CAN ATTRACT BUSINESS AND REDUCE RISK AND TIME-TO-MARKET CUSTOMER IP Design Center Foundry IP ASIC/FPGA 13 13
AN OPEN COMPETITIVE MARKET EXISTS CUSTOMER PORTABLE IP Standards: REPOSITORY (Multiple www.vsia.org www.design-reuse.com Suppliers) www.ieee.org Foundry Foundry Foundry ASIC/FPGA 14 14
FREE OPEN-SOURCE CORES • LEON is an open-source 32-bit SPARC V8 CPU that was developed by the European Space Agency and is available for free at www.gaisler.com • Other cores at www.opencores.org • Other cores at www.opencores.org – USB 2.0 – USB 2.0 – Ethernet MAC – Ethernet MAC – DES/AES Encryption – DES/AES Encryption – FIR/IIR Filters – FIR/IIR Filters – Floating Point Unit – Floating Point Unit 15 15
QUALITY INTELLECTUAL PROPERTY • The VSI (Virtual Socket Interface) Alliance (VSIA) is an open, international organization that includes representatives from all segments of the SoC industry: System houses, Semiconductor vendors, Electronic Design Automation (EDA) companies, and Intellectual Property (IP) providers. VSIA's mission is to dramatically enhance the productivity of the SoC design community. • Quality Intellectual Property (QIP) Metric v3.0 is available for free from the VSIA website: www.vsia.org 16 16
QIP METRICS 17 17
DEVELOPING QUALITY IP • Requirements should be mapped into an executable specification which produces the desired golden reference responses. • HDL and FPGA responses must match the golden responses identically. MATLAB or C RESPONSES (fixed point) (golden ref.) RESPONSES STIMULI HDL SOURCE CODE (simulation) RESPONSES FPGA (system) 18 18
THE TESTBENCH CONTAINS THE STIMULI, RESPONSES AND UUT • Functional stimuli are developed by the designer to mimic the system environment. • The tester is written in HDL but is not synthesized into the FPGA. Testbench (Tester + HDL Source Code) Testbench (Tester + HDL Source Code) Tester Tester STIMULI RESPONSES HDL SOURCE CODE (manual) 19 19
RAPID VERIFICATION SAVES TIME • Minimizing time-to-market encourages designers to develop only a few tests for simulation and then proceed to testing the design inside the FPGA in its real-world environment. The FPGA executes tests 500x faster than the simulator and the real-world system environment produces the tests automatically. Tester Tester STIMULI RESPONSES HDL SOURCE CODE (manual) SIMULATION REAL-WORLD SYSTEM ENVIRONMENT STIMULI RESPONSES FPGA (auto) (actual) 20 20
CONTROLLABILITY AND OBSERVABILITY AID DEBUGGING • When errors are encountered on the FPGA board where tests are limited to the primary inputs and primary outputs, the designer can return to simulation where complete controllability and observability of all of the internal nodes are available for debugging. Primary Logic Inputs Gate Logic Primary Primary Output Gate Inputs Logic Internal Gate Nodes Primary Outputs 21 21
POLISHING FOR REUSE • Once the HDL source code has been verified in the FPGA, the design can be polished for reuse. • This involves documenting the HDL and providing test access mechanisms for reuse as an embedded core per IEEE 1500: http://grouper.ieee.org/groups/1500 • Also, the tester code should be enhanced with assertion-based tests to achieve the desired HDL code coverage. • Constrained, random-generated tests can be produced automatically for large HDL cores. 22 22
COVERAGE-DRIVEN TESTS The simulator can produce coverage reports and identify missed statements in the code. 23 23
ASSERTION-BASED VERIFICATION The tester code should include stimuli and responses. The tester code should include stimuli and responses. “Failure” stops simulation while “warning” does not. “Note” is used to document a correct response. wait_clock(16); wait_clock(16); IF (left_seg = X"6") IF (left_seg = X"6") -- check second state of 7-segment display -- check second state of 7-segment display THEN THEN ASSERT false ASSERT false REPORT "Output signals set correctly (7-segment second state)" REPORT "Output signals set correctly (7-segment second state)" SEVERITY note; SEVERITY note; ELSE ELSE ASSERT false ASSERT false REPORT "Output not set correctly (7-segment second state)" REPORT "Output not set correctly (7-segment second state)" SEVERITY warning; SEVERITY warning; END IF; END IF; 24 24
BUILT-IN SELF-TEST CODE • The HDL source code can be augmented with Built-In Self-Test (BIST) code. • BIST code can verify that the I/O and other likely failure modes are working properly or not. • BIST code can also include functional test cases to assure proper operation before execution or during “idle” times. 25 25
GRAPHICAL TOOLS CAN REUSE AND CREATE IP BLOCKS • Library cells (basic IP blocks) are integrated into a larger block that itself can be reused. 26 26
ACQUIRING IP • STAR IP: Blocks requiring 100+ staff years to design (like ARM, MIPS ) have become bestsellers and come with lots of support. • Small IP: Blocks requiring 1-2 staff years to design are priced at 1/3 of the development cost. Buyers are skeptical about the value and often prefer to do these in-house. • Medium IP: Blocks requiring 5-10 staff years are profitable for both seller and buyer. However, some suppliers have been bought by foundries to add to the foundries’ captive portfolios. 27 27
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