Chair of Network Architectures and Services Department of Informatics Technical University of Munich Cost Efficient Hardware Timestamping Intermediate Presentation Alexander Frank June 6, 2018 Chair of Network Architectures and Services Department of Informatics Technical University of Munich
Chair of Network Architectures and Services Department of Informatics Technical University of Munich Contents Motivation Test Setup Packet Matching Comparison with other solutions Outlook Frank – Networking 2
Chair of Network Architectures and Services Department of Informatics Technical University of Munich Motivation For conducting high precision latency measurements one currently has the following options: • Proprietary solutions (e.g. DAG Packet Capture Cards from endace 1 ) • NetFPGAs For this IDP we take a different approach using only commodity hard- ware The Intel Xeon Processor D-1500 family offers 10 GbE connections based on X552 Ethernet Controllers → able to timestamp arbitrary packets 1 https://www.endace.com/endace-high-speed-packet-capture-solutions/oem/dag/ Frank – Networking 3
Chair of Network Architectures and Services Department of Informatics Technical University of Munich Current set-up Splitter Narva Klaipeda Tilga Figure 1: All connections are optical fiber based, splitters are completely passive and do disturb communication Frank – Networking 4
Chair of Network Architectures and Services Department of Informatics Technical University of Munich Explanation – Klaipeda, Narva Narva: • MoonGen and DPDK as gen- erator • Generates up to 10 Gbit/s Narva • Rate limiter to achieve desired bit rate Klaipeda: • MoonGen forwarder Klaipeda • Open vSwitch • Any other forwarding/routing Figure 2: Narva (Generator) and Klaipeda (DuT) software Frank – Networking 5
Chair of Network Architectures and Services Department of Informatics Technical University of Munich Explanation – Tilga Tilga features an X552 which allows timestamping of arbitrary packets • Captures packets • Inserts hardware timestamps • Optionally handles post- Tilga processing The cables from Tilga to the splitter Figure 3: Sniffer, captures and/or box have the same length timestamps packets → no relative error Frank – Networking 6
Chair of Network Architectures and Services Department of Informatics Technical University of Munich Packet Matching Table Size Table Size Pre DuT Post DuT Packet Packet 10 Gbit/s ≈ 14.88 mpps ID: 5 ID: 3 Table size = 2^28 Entries Port 0 Port 1 => Max. latency ≈ 18 sec Sniffer: Tilga Packet Higher latencies with ID: 5 increased table size Table Packet with ID: 4 Packet Packet 2^28 Latency ID: 3 ID: 3 Entries Packet ID: 3 Packet ID: 2 ≥ 5 Bytes 8 Byte Packet Headers ID: 1 Payload with ID Hardware Timestamp (e.g. Eth, IPv4, UDP) Frank – Networking 7
Chair of Network Architectures and Services Department of Informatics Technical University of Munich Operation Modes 1. Online Latency is computed during capture operation. Low accuracy. 2 2. Offline Timestamps Only Latency is computed in a separate processing step. During cap- ture only the timestamps and IDs are saved. High accuracy. 2 3. Offline Packet Capture All incoming packets are captured. Postprocessing tries to find matching packets according to user-defined function. High accu- racy. 2 Requires packet payload to contain an ID Frank – Networking 8
Chair of Network Architectures and Services Department of Informatics Technical University of Munich Comparison Device Timestamp Ports Price User Resolution (USD) friendly? Endace DAG 10X2-S 3 4 ns 2 2500 ( � ) NetFPGA SUME 4 6.25 ns 4 4100 X Intel Xeon CPU D-1537 5 12.5 ns 2 570 � Conclusion: Using commodity hardware we achieve reasonable pre- cise timestamps for a fraction of the cost 3 https://www.endace.com/endace-high-speed-packet-capture-solutions/oem/dag/ 4 https://netfpga.org/site/#/systems/1netfpga-sume/details/ 5 https://ark.intel.com/de/products/91196/Intel-Xeon-Processor-D-1537-12M-Cache-1_70-GHz Frank – Networking 9
Chair of Network Architectures and Services Department of Informatics Technical University of Munich Baseline – 30 m fiber cable Frank – Networking 10
Chair of Network Architectures and Services Department of Informatics Technical University of Munich Next Steps Modes: Online Done Offline Timestamps Only Done Offline Packet Capture WIP Other: Post-processing Done Automated Measurement Series Done Documentation Pending Frank – Networking 11
Chair of Network Architectures and Services Department of Informatics Technical University of Munich Questions and Suggestions? Frank – Networking 12
Chair of Network Architectures and Services Department of Informatics Technical University of Munich Latency – MoonGen forwarder Frank – Networking 13
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