Commercial CAD: Challenges and Opportunities Ted Vucurevich CTO – Advanced Research and Development Cadence Design Systems 1
•Commercial CAD: Today’s Problems •Tomorrow’s Opportunities •Conclusions Agenda 2
Quiz #1 Commercial CAD is? 1. Too Expensive 2. Too Late to solve my “real” problems 3. Too Complicated 4. Too Important to ignore Answer: It Depends on your viewpoint 3
Many Late-Era CMOS Silicon Challenges Feature size & spacing Very low supply voltages approach lithography limits Defect yields, process Increasing leakage power, pervasive signal integrity variation impacts, design issues rule complexity Pipelined HW / SW Design cost 4X vs. 130nm Co-Design mandatory Mask costs 2X vs. 90nm Scalability of EDA infrastructure, Guardbands and process variation low-power design techniques, analog consume much of clock cycle, some and digital together, handling analog IP new design techniques needed Very high-performance chips Very large chips (100MG+) (1GHz+) 4
What is Manufacturable? Design Rule Complexity 4 3 Normalized 2 Pages 1 0 250 nm 180 nm 130 nm 90 nm 65 nm Node Increasing lithographic complexity is driving increasingly complex design rules. Source: Mark Mason (TI) 5
Modeling at 65nm and beyond 3d Pattern Based Modeling Net to Extract � Sidewall capacitance dominates � Complex 3D structures Source: David Overhauser 6
Who’s my neighbor? Physical Data Organization must evolve What’s in the Box? 7
Runtime SW Dependent Variability is a First Class design concern Spot Hot 25% Isub 1 Atom = 8
Next Gen Architecture will be needed Applications Control Drivers Control and coordination of the Engines Component Software Integration mechanism Component Plug-in Synthesizers � Re-entrant Components Analyzers Modelers Verifiers � Heterogeneous � Incremental � Hierarchical � Peer - Peer Transaction layer Data Thread Safe Run-time Data transactions Open Access Unified Persistent Data Model 9
Multi-Objective Optimization Necessary Runtime Area Timing Old Dynamic DFT Leakage Power Power Approach 15% 85% Typical 2x to 5x faster Timing Global Timing Parallel Area Approach Global Area Dynamic Power Inc Multi- Leakage Power Global map 75% 25% Remap Dimension DFT 8% Global map 66% Inc 26% Slack Old synthesis = -2.893ns Consumer Device • 500k gates + 10 RAMs RC w/ scan, power = -0.384ns • 130nm process 8.10mm 2 Die Size 6.01 • 5 clocks 9.07mm 2 mW 13.9 – Fastest=200MHz mW Leakage Power 10
The CAD Eco-System is changing Tomorrow Today Customer Customer Integration Differentiation Integration 11
Answers to the most pressing questions about Commercial CAD today: 1. 3.5 2. The ones you would expect 3. Yes 4. No 5. Yes. Micro and Nano Systems 6. 42 12
•Commercial CAD: Today’s Problems •Tomorrow’s Opportunities •Conclusions Agenda 13
It’s the System Stupid Macro-Systems Meters Micro-Systems Centimeters Nano-Systems Millimeters 1891 1947 1993 14
Source: Jan Rabaey UCB Electronic System and Architectural Design 15
Micro-Chips to Micro-Systems Mem ory Bio-Sensor Flash Mem ory DRAM Logic/ Cores 2nd IC Level TSV (drawn) Direct Bond 1st IC Level Ziptronix 3D Systems System-in-Package (SiP) 16
MicroFluidics: Answers for Power? “Firebolt ™” Chip level Thermal Analysis The researchers concluded it should be possible to remove a heat flux of 100 W/cm2 with a pressure drop of <2 atmospheres. Microfluidic Channels (Source: Georgia Institute of Technology) 17
Photonics: Next-Gen Micro-Optical Systems SOI MOS WaveGuide Luxtera 10Gbit CMOS Photonics Platform 18
Lab-on-a-chip: Next-Gen Micro-Bio Systems 19
Next-Gen Molecular Analysis 20
Carbon Nano-tube Manufacturing Nano-Systems: The Next Frontier Artificial Blood: Robert A. Freitas Jr. 21
Evolving CMOS: One material at a time 1mb Molecular DRAM Gate 1.2nm SiO2 ~1nm ZettaRam Memory Silicon Substrate Cell Molecular Storage Element Molecular Material 65nm Gate Oxide 22
Nano Computing Gates: Wires: NanoFabrics NanoTubes = + Devices: Memory, Gates GigaGate Capacity! After: Butts, DeHon, and Goldstein (ICCAD 2002) ZettaCore Memory 23
Moore’s Law: You haven’t seen anything yet! doubles every 1.E+11 few months? Ops/sec/$ nanometer 1.E+10 1.E+09 doubles every 1.5 years 1.E+06 Tubes/ CMOS Transistor 1.E+03 Mechanical / Relays 1.E+00 doubles every doubles every 7.5 years 2.3 years 1.E-03 Seth Copen Goldstein (CMU) 1.E-06 1880 1900 1920 1940 1960 1980 2000 2010 203 2020 0 24
•Commercial CAD: Today’s Problems •Tomorrow’s Opportunities •Conclusions Agenda 25
Conclusions: More Answers than Questions •No •Tremendous Opportunities in Micro and Nano Systems •Modeling, Analysis, Optimization •EE’s, CS’s, Bio, Chemical, Medical, Mechanical, Optical, Physics, Mathematics •Yes 26
Conclusion: The Whole Story • Is Commercial EDA Dead? – No • Why not? – Tremendous Opportunities in Micro and Nano Systems • In what fundamental areas? – Modeling, Analysis, Optimization • What will the micro and nano-system design teams look like? – EE’s, CS’s, Bio, Chemical, Medical, Mechanical, Optical, Physics, Mathematics • Are you glad you are still in CAD? – Yes!!! 27
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