Clock Tree Construction based on Arrival Time Constraints Rickard - PowerPoint PPT Presentation

Clock Tree Construction based on Arrival Time Constraints Rickard Ewetz, University of Central Florida Cheng-Kok Koh, Purdue University

Clock Tree Synthesis Clock Source • Objective: Connect source to sinks wire • Buffers • Wires buffer • Constraints: • Transition time • Skew Clock Sinks D Q D Q D Q D Q a b c d

Timing Constraints t S max t CQ t t t j j i ij i     CQ max S u T t t t ij i ij j Combinational FF j Q Q D    FF i D H CQ min l t t t logic ij j i ij    l t t u CQ t m in H ij i j ij t t i   j ij l skew u ij ij ij 𝐷𝑅 + 𝑢 𝑗𝑘 𝑛𝑏𝑦 + 𝑢 𝑘 𝑇 ≤ 𝑢 𝑘 + 𝑈 𝑢 𝑗 + 𝑢 𝑗 𝐷𝑅 + 𝑢 𝑗𝑘 𝑛𝑗𝑜 ≥ 𝑢 𝑘 + 𝑢 𝑘 𝐼 𝑢 𝑗 + 𝑢 𝑗

Skew Constraint Graph (SCG) 𝑚 12 ≤ 𝑢 1 − 𝑢 2 ≤ 𝑣 12 𝑥 12 = 𝑣 12 FF 2 Q D 𝑚 24 ≤ 𝑢 2 − 𝑢 4 ≤ 𝑣 24 2 1 4 FF 4 Q D FF 1 D Q 3 𝑚 34 ≤ 𝑢 3 − 𝑢 4 ≤ 𝑣 34 𝑥 21 = −𝑚 12 FF 3 Q D 𝑚 13 ≤ 𝑢 1 − 𝑢 3 ≤ 𝑣 13 𝑢 1 − 𝑢 2 ≤ 𝑣 12 𝑢 𝑗 − 𝑢 𝑘 ≤ 𝑥 𝑗𝑘 𝑚 12 ≤ 𝑢 1 − 𝑢 2 𝑢 2 − 𝑢 1 ≤ −𝑚 12

Outline • Timing constraints • Outline • Previous works • Proposed approach • Proposed techniques • Clock tree construction based on arrival time constraints • Specification of arrival time constraints • Methodology • Experimental results

𝑊 (|𝑊| − 1|) Timing Constraints 2 Dynamic implied skew constraints [17] SCG Static equal arrival time constraints [13] −𝑒 21 𝑒 21 |V| static arrival −𝑒 31 𝑒 13 time constraints 2 −𝑒 41 𝑒 14 1 4 Static useful arrival time constraints [11] −𝑒 32 𝑒 23 −𝑒 42 𝑒 24 3 𝑒 34 −𝑒 43 𝑢 3 − 𝑢 4 = 𝑡𝑙𝑓𝑥 34 = 𝑏 Static bounded arrival time constraints [5] −𝑒 21 𝑒 21 2 −𝑒 31 𝑒 13 −𝑒 41 𝑒 14 1 4 Static bounded useful arrival time constraints [2] 𝑥 34 = 𝑏 −𝑒 32 𝑒 23 3 −𝑒 42 𝑒 24 𝑥 43 = −𝑏 𝑒 34 −𝑒 43 used in this work

Timing constraints Static arrival time constraints Dynamic implied skew constraints 𝑚𝑐 ≤ 𝑦 𝑗 𝑣𝑐 , 𝑒 𝑘𝑗 ≤ 𝑢 𝑗 − 𝑢 𝑘 ≤ 𝑒 𝑗𝑘 𝑦 𝑗 ∀𝑗 ∈ 𝑊 𝑣𝑐 − 𝑦 𝑘 𝑚𝑐 ≤ 𝑥 𝑗𝑘 , 𝑦 𝑗 ∀(𝑗, 𝑘) ∈ 𝐹 𝑣𝑐 , 𝑚𝑐 , 𝑦 𝑗 𝑢 𝑗 ∈ 𝑦 𝑗 ∀𝑗 ∈ 𝑊 [2] C. Albrecht, B. Korte, J. Schietke, and J. Vygen. Maximum mean weight cycle in a digraph and minimizing cycle time of a logic chip. Discrete Applied Math., 123(1-3):103 – 127, 2002. [5] J. Cong, A. B. Kahng, C.-K. Koh, and C.-W. A. Tsao. Bounded-skew clock and Steiner routing. ACM Trans. Des. Autom. Electron. Syst., 3(3):341 – 388, July 1998. [11] J. Fishburn. Clock skew optimization. IEEE Transactions on Computers, pages 945 – 951, 1990. [13] R.-S. Tsay . Exact zero skew. In ICCAD’91, 1991. [17] C.-W. A. Tsao and C.-K. Koh. UST/DME: a clock tree router for general skew constraints. TODAES, pages 359 – 379, 2002. [12] S. Held, B. Korte, J. Massberg, M. Ringe, and J. Vygen. Clock scheduling and clock tree construction for high performance asics . ICCAD’03, pages 232– 239, 2003.

Previous Works – ZST and UST in [11,13] 𝑢 𝑗 == 𝑢 𝑘 Static equal arrival time constraints 𝐺𝑁𝑆 𝑙 Deferred Merge Embedding (DME) k Static useful arrival time constraints 𝑢 𝑗 = 0 𝑢 𝑘 = 0 ZST: UST: 𝑢 𝑗 = 𝑝𝑔𝑔 𝑢 𝑘 = 𝑝𝑔𝑔 𝑗 𝑘 𝑝𝑔𝑔 - Low timing margin utilization 1 + Useful skew [11] J. Fishburn. Clock skew optimization. IEEE Transactions on Computers, pages 945 – 951, 1990. [13] R.-S. Tsay . Exact zero skew. In ICCAD’91, 1991.

Previous works – BST in [5] 𝑛𝑏𝑦 − 𝑢 𝑙 𝑛𝑗𝑜 ≤ 𝐶 𝑢 𝑙 𝐺𝑁𝑆 𝑙 DME Static bounded arrival time constraints k B 𝑛𝑗𝑜 = 0 𝑛𝑗𝑜 = 0 𝑢 𝑗 𝑢 𝑘 𝑛𝑗𝑜 = min{𝑢 𝑗 𝑛𝑗𝑜 + 𝑥 𝑙, 𝑗 , 𝑢 𝑘 𝑛𝑗𝑜 + 𝑥 𝑙, 𝑘 } 𝑢 𝑙 𝑛𝑏𝑦 = 0 𝑛𝑏𝑦 = 0 𝑢 𝑗 𝑢 𝑘 𝑛𝑏𝑦 = max{𝑢 𝑗 𝑛𝑏𝑦 + 𝑥 𝑙, 𝑗 , 𝑢 𝑘 𝑛𝑏𝑦 + 𝑥 𝑙, 𝑘 } 𝑢 𝑙 + Medium timing margin utilization + Rerooting - No useful skew [5] J. Cong, A. B. Kahng, C.-K. Koh, and C.-W. A. Tsao. Bounded-skew clock and Steiner routing. ACM Trans. Des. Autom. Electron. Syst., 3(3):341 – 388, July 1998.

Previous works n=5 n=4 BST in [5] 1 2 3 4 5 6 Rerooting to (2m -3) Rerooting to (2n -3) 1 2 3 4 5 6 2 1 4 3 1 2 3 4 3 4 3 4 1 2 1 2 5 6 5 6 1 2 3 5 6 5 6 4 5 6 2 1 4 3 1 2 3 4 3 4 3 4 1 2 1 2 [5] J. Cong, A. B. Kahng, C.-K. Koh, and C.-W. A. Tsao. Bounded-skew clock and Steiner routing. ACM Trans. Des. Autom. Electron. Syst., 3(3):341 – 388, July 1998.

Previous works - UST in [2,12] Static bounded useful arrival time constraints A FMR exists but not used + High timing margin utilization The length was + Useful skew Lexicographically - Interconnect delay not considered during merging maximized [2] C. Albrecht, B. Korte, J. Schietke, and J. Vygen. Maximum mean weight cycle in a digraph and minimizing cycle time of a logic chip. Discrete Applied Math., 123(1- 3):103 – 127, 2002. [12] S. Held, B. Korte, J. Massberg, M. Ringe, and J. Vygen. Clock scheduling and clock tree construction for high performance asics . ICCAD’03, pages 232– 239, 2003.

Previous Works – UST in [2,12] 𝑢 1 − 𝑢 2 ≤ 40 40 𝑢 2 − 𝑢 3 ≤ 40 20 100 220 𝑢 3 − 𝑢 1 ≤ 220 40 100 100 [2] C. Albrecht, B. Korte, J. Schietke, and J. Vygen. Maximum mean weight cycle in a digraph and minimizing cycle time of a logic chip. Discrete Applied Math., 123(1- 3):103 – 127, 2002. [12] S. Held, B. Korte, J. Massberg, M. Ringe, and J. Vygen. Clock scheduling and clock tree construction for high performance asics . ICCAD’03, pages 232– 239, 2003.

Previous works – UST in [17,6] 𝐺𝑇𝑆 𝑗𝑘 = [−𝑒 𝑘𝑗 , 𝑒 𝑗𝑘 ] • Computing FSR + update SCG • 𝑃 𝑊 2 in [17] 𝐺𝑁𝑆 𝑗𝑘 • 𝑃(𝑊 log 𝑊 + 𝐹) in [6] DME + Full timing margin utilization - Update of timing constraints required [17] C.-W. A. Tsao and C.-K. Koh. UST/DME: a clock tree router for general skew constraints. TODAES, pages 359 – 379, 2002. [6] R. Ewetz, S. Janarthanan, and C.-K. Koh. Fast clock skew scheduling based on sparse-graph algorithms. ASP- DAC ’15, pages 472– 477, 2014.

Previous works - Summary *denotes that rerouting was not applied but would be easy to perform Tree Constraints Update Ease of exploring Useful Degree of Considers construction Required? topologies based on skews timing interconnect proposed in rerouting allowed margin delays during merging utilization [13] Static equal arrival time [13] No easy* No Low Yes [13] Static useful arrival time [11] No easy* Yes Low Yes [5] Static bounded arrival time [5] No easy No Medium Yes [12] Static bounded useful arrival time [2] No `n/a’ Yes High No [17] Dynamic implied skew [17] Yes difficult Yes Full Yes This paper Static bounded useful arrival time [2] No easy Yes High Yes [2] C. Albrecht, B. Korte, J. Schietke, and J. Vygen. Maximum mean weight cycle in a digraph and minimizing cycle time of a logic chip. Discrete Applied Math., 123(1-3):103 – 127, 2002. [5] J. Cong, A. B. Kahng, C.-K. Koh, and C.-W. A. Tsao. Bounded-skew clock and Steiner routing. ACM Trans. Des. Autom. Electron. Syst., 3(3):341 – 388, July 1998. [11] J. Fishburn. Clock skew optimization. IEEE Transactions on Computers, pages 945 – 951, 1990. [13] R.-S. Tsay . Exact zero skew. In ICCAD’91, 1991. [17] C.-W. A. Tsao and C.-K. Koh. UST/DME: a clock tree router for general skew constraints. TODAES, pages 359 – 379, 2002. [12] S. Held, B. Korte, J. Massberg, M. Ringe, and J. Vygen. Clock scheduling and clock tree construction for high performance asics . ICCAD’03, pages 232– 239, 2003.

Proposed approach • Construct a clock tree • Minimum wire length and buffer area • Arbitrary skew constraints • Proposed Approach • Construct a clock tree meeting bounded useful arrival time constraints • Specify the constraints to minimize cost

𝑛𝑗𝑜 = − 𝐶 𝑤 𝑚𝑐 𝑝𝑔𝑔 2 − 𝑦 𝑗 𝑗 Proposed Clock Tree Construction 𝑛𝑏𝑦 = 𝐶 𝑤 𝑣𝑐 𝑝𝑔𝑔 2 − 𝑦 𝑗 𝐶 𝑤 𝑗 𝑛𝑏𝑦 = 𝐶 𝑤 2 𝑣𝑐 𝑝𝑔𝑔 2 − 𝑦 4 𝑣𝑐 𝑦 4 4 𝑣𝑐 𝑦 2 𝑣𝑐 𝑦 1 𝑣𝑐 𝑦 3 Proposed clock 𝑚𝑐 𝑦 4 0 tree construction 𝑚𝑐 𝑦 1 𝑚𝑐 𝐶 𝑤 𝑦 3 𝑚𝑐 𝑦 2 𝑛𝑗𝑜 = 𝑝𝑔𝑔 𝑛𝑗𝑜 𝑢 𝑗 𝑗 𝑛𝑏𝑦 = 𝑝𝑔𝑔 𝑛𝑗𝑜 = − 𝐶 𝑤 𝑛𝑏𝑦 𝑢 𝑗 𝑚𝑐 𝑗 𝑝𝑔𝑔 2 − 𝑦 4 4 𝐶 𝑤 - 2

Specifying arrival time constraints • Objectives: 𝑡𝑙𝑓𝑥 (3) • Valid constraints • min and max 𝑚𝑐 𝑣𝑐 𝑦 𝑗 𝑦 𝑗 𝑡𝑙𝑓𝑥 (2) • Alignment 𝑡𝑙𝑓𝑥 (3) • Similar lengths 2 𝑡𝑙𝑓𝑥 (1) 𝑡𝑙𝑓𝑥 (2) 2 𝑡𝑙𝑓𝑥 (1) 2 −𝑡𝑙𝑓𝑥 (1) 2 −𝑡𝑙𝑓𝑥 (2) 2