Circuits in Emerging Nanotechnologies Rinaldo Castello University - PowerPoint PPT Presentation

Circuits in Emerging Nanotechnologies Rinaldo Castello University of Pavia Thomas Ernst CEA-LETI Seok-Hee Lee SK-Hynix Subhasish Mitra Stanford University Ion O’Connor Ecole Centrale de Lyon Chair: Adrian Ionescu, EPFL

Rinaldo Castello University of Pavia

Thomas Ernst CEA-LETI

FROM INTEGRATED CIRCUITS TO INTEGRATED SYSTEMS THOMAS ERNST Montreux Symposium on emerging trends in electronics 1/12/2014

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Seok-Hee Lee SK-Hynix

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Memory demand split across multiple sub-segments @!B$0&,*E!./!-,B&#,!J&%%!$22,$0!$'-!+&(+!2,0/.01$'#,!R!%.J!2.J,0!! TY@9!J&%%!F,!',,-,-!$4!.',!./!*+,!1.4*!&12.0*$'*!0.%,4!&'!*+,!4E4*,1! Low Cost R"F&$(Q$*((R&?-?3&(VR"F(W"F&$X Automotive Smart Devices PC / Server DRAM Wearable Low Power High Speed Devices Higher Tr. Performance (High Speed)

Transistor for Higher performance & Lower Power U,,-4!+&(+,0!2,0/.01$'#,!2,0&2+,0$%!*0$'4&4*.0!/.0!TY@9!$'-!&*!&4!$j,#*,-!FE!*+,!4%.J!4#$%,K -.J'!*0,'-!./!M.Z! Jox Limit for Logic Tr [Source : ITRS 2003~2007] DRAM Tr Nitrided SiO2 Jox Limit for DRAM Tr 25nm node Jox [A/cm2] Tox [ Å ] HKMG Logic Tr HKMG Tox [ Å ] Gate Length of Peripheral Tr. [nm]

Low Power DRAM design Technique example ^$0&.54!#&0#5&*!*,#+'&r5,!&4!F,&'(!4*5-&,-!/.0!%.J!2.J,0!TY@9 Power Gating Multi-VTH Dynamic Body Bias Reduce leakage currents by inserting a Reduce leakage power where speed Controlling body bias, high speed & lo Objective switch transistor into the logic stack is not needed by high Vt transistor w leakage current can be achieved Q&(+!"2,,-N!Q&(+!V,$`$(,! >%.#`!4&('$% L Vdd T,%$E!%&', Logic L Vdd Cell L L >.12$0$*.0 L L L L T,#.-,0 Logic Virtual Scheme Cell Ground 8&$4!o,'A Y,-5#,-!"2,,-N!V.J!V,$`$(,! Switch @12 sleep Cell H ^ TT ^ "" H L L L L V"7 L L k".50#,!6!V.J!L.J,0!T,4&('!9,*+.-.%.(E!$'-!T,4&('!W%.JK!l@U!9A!Y@8@?m! !!R!9A!9&E$n$`&!,!$%N!@!IAGo7L"_p!5L0.#!54&'(!42,,-K$-$2PB,!^*!>9X"q

Solutions for Higher Performance & Higher Density Y,r5&0,!+&(+,0!42,,-N!%,44!7_X4!4#+,1,!-5,!*.!20.#,44!-&s#5%*E!$'-!+&(+!#.4*!./!M"^ � TSV-Stacking Density # High Density � Conventional Stacking High performance # High Density, Low power Low Performance # but, High Cost & Process Difficulty Wire Bonding [16Gb TSV, SK Hynix : 40nm 2Gb x 8] � Memory Requirements . Lower Power � Non-Stacking . Higher Performance # High Performance, Low Density . Higher Density Performance

High Reliability & Low Cost DRAM Y,r5&0,!#.4*!0,-5#P.'!*+0.5(+!-,#0,$4&'(!-,/,#*!0$*,!FE!X'K>+&2!?>>N!LLYN!,*#A Item Objective Effect, Status Issues Compensate Retention Time Degr Advanced Refresh Refresh Increase IDD adation Smart Refresh Refresh Improve LtRAS VBB Temp Modulation Write Write Recovery Time DFR (Design For cell Reliabilit y) POD (Post Over Drive) Refresh Compensate Sensing Margin Increase IDD On chip ECC Error Correction Area Overhead PPR (using ARE) Error Aging Fail

Subhasish Mitra Stanford University

The Next 1,000X Subhasish Mitra Collaborator: H.-S. Philip Wong Department of EE & Department of CS Stanford University

Abundant-Data Applications 27

N3XT 1,000X Energy Efficiency 3D Resistive RAM Massive storage Monolithic 3D Carbon nanotube FET compute elements Inter-layer vias: thermal STTRAM 1,000X TSV L2, L3, … density Carbon nanotube FET (or even silicon) thermal compute elements 1. All data active on-chip 2. Computation immersed in memory 3. Variability, yield, reliability 28

Carbon Nanotube FET (CNFET) 1. First CNFET computer CNT: d = 1.2nm CNFET d 2. High-performance CNFETs I ON ( ! A/ ! m) Sub-litho CNFET Si FETs pitch (Stanford fab) (foundries) 29 [Shulaker Nature 13, ISSCC 13, IEDM 14]

First CNT Monolithic 3D IC Conventional vias, Process temp. no TSVs < 250 o C Logic + memory Inter-layer digital circuits CNT 3 CNFETs V OUT (V) 2 Resistive RAM 1 Resistive RAM Silicon FETs V IN (V) 0 0 1 2 3 30 [Wei IEDM 13, Shulaker VLSI Tech. 14, IEDM 14]

Ian O’Connor Ecole Centrale de Lyon

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