Chronopixel CMOS Sensor Development for the ILC Jim Brau , Nikolai Sinev, David Strom University of Oregon, Eugene, Oregon Oliver Baker, Charles Baltay, Christian Weber ❋ Yale University, New Haven, Connecticut EE work has been contracted to Sarnoff Corporation/SRI ❋ current address: Brookhaven National Laboratory Note: Many of these slides are based on originals prepared by Nikolai Sinev and Christian Weber
International Linear Collider First stage - 250 GeV (Higgs Factory) Ultimately higher energy: 0.5 - 1 TeV SiD at ILC Damping Ring ILC250 e- Source e+ Main Linac ~20km e+ Source e- Main Linac CPAD Workshop, December 10, 2019, Madison Jim Brau 2
Higgs precision Higgs at the ILC 3.5 Precision of Higgs boson couplings [%] Model Independent EFT Fit LCC Physics WG × 1/2 HL-LHC ILC250 ⊕ “Model-independent” 3 HL-LHC ILC250 ILC500 ⊕ ⊕ 1/10 × EFT fit dark/light: S1*/S2* 1/3 × 2.5 1/2 × 2 ~1 % required 1.5 to access New Physics 1 beyond HL-LHC 0.5 direct search 0 Z W b g c Z t τ Γ Γ γ γ µ λ inv h arXiv:1903.01629 Highly model-independent analysis of EFT: Phys Rev D97, 053003 (2018) CPAD Workshop, December 10, 2019, Madison Jim Brau 3
M. Yamauchi, April 8, Lausanne Processes and Approximate Timelines Toward Realization of ILC (Physicists’ view) 2020.5 2018.12 2019.3 2024- Agreement on governance, Discussion among governments operation, sharing of cost by Japanese government Exchange of information and human resources Strengthen US-Japan Discussion Group, Start construction of ILC Announcement cost reduction R&D, Full-scale negotiation among governance discussion governments – specification of Government Level conditions and processes Summarize Final agreement among governments MEXT Critical decision Start negotiations among governments panel opinions of Establish Discussion Group with process relevant the European partners ministries on international sharing on construction the preparation phase under approval by each Oct. 2019 Next Roadmap MOU among research labs on start of by MEXT SCJ committee on ILC SCJ Master Plan 3/7 government Physicists Level LCB/ICFA mtgs. @ Tokyo EPPSU submitted to CERN ILC pre-lab (4 years) European Particle Physics Strategy Update Establish KEK International WG Draft proposal by researchers Produce draft for international sharing of human and material resources on international cost sharing Talks with other countries Good enough design for the final approval of construction, resolution of remaining technical issues ＊ ICFA: international organization of researchers consisting of directors of world’s major accelerator labs and representatives of researchers ＊ ILC pre-lab: International research organization for the preparation of ILC based on agreements among world’s major accelerator labs such as KEK, CERN, FNAL, DESY etc.
Status of ILC decision in Japan ■ Legislative branch (Diet) strongly supports hosting ILC in Japan. ■ Two final national steps are needed to reach decision. ■ (1) Science Council of Japan (SCJ) calls for proposals of large-scale research projects every three years, and recommends “priority programs” to MEXT. In the latest process in 2017, 20 programs were selected from 200 proposals. ■ ILC will be evaluated for first time this year to provide evidence of support by broader Japanese academics. ■ SCJ selected ILC for the reduced long list after 1/3 selection and invited ILC for an “interview.” ■ Results of final SCJ evaluation will be publicized officially in February 2020. ■ (2) Next step will be MEXT Roadmap in 2020. Previous 2017 Master Plan/Roadmap process, MEXT made its own selection starting from the SCJ long list to create MEXT Roadmap. CPAD Workshop, December 10, 2019, Madison Jim Brau 5
ILC vertex detector requirements ILC Beam environment: Bunch crossing rate (Collisions rate) ~3 MHz Number of bunches in bunch train up to ~3000 (first 250 GeV stage 1312) Bunch trains interval – 200 ms. (5 Hertz) Detector System 5 layers, ~2.4 cm - ~ 10 cm. Length: ~20 cm with forward discs. Pixel size < 15x15 µ m 2 (space point resolution ~3.5 µ ). Each pixel has 2x12 bit memory buffer to record 2 time stamps during bunch train. Room temperature operation with forced air cooling and non-turbulent air flow. Power dissipation for entire Vertex Detector to <~ 100 W. Sparse readout allows full readout in 200 ms. S/N ratio should be more than 30 (noise less than 25 e - ). CPAD Workshop, December 10, 2019, Madison Jim Brau 6
Chronopixel development history 2004 –First discussion with Sarnoff Corporation. Oregon University, Yale University and Sarnoff Corporation collaboration formed. Chronopixel prototype 3 2007-2010 - Prototype 1 5x5 mm chips, 80 each, containing 80x80 50 µ m mm ~1.2 Chronopixels array TSMC 0.18 µ m ⇒ ~50 µ m pixel Epi-layer only 7 µ m Low resistivity silicon (~10 ohm-cm) 2010-2013 - Prototype 2 MOSIS / TSMC. (48x48 array of 25 µ m pixel, 90 nm process) 2014- Prototype 3 CPAD Workshop, December 10, 2019, Madison Jim Brau 7
Summary of prototypes 1 and 2 tests Prototype 1 demonstrated: • Time stamp recording with 300 ns period (1 ILC bunch crossing interval) • System to read all hit pixels during 200 ms interval between bunch trains (by implementing sparse readout) • Pulsed power (2 ms ON and ~200 ms OFF) with preserved comparator performance. • Noise figure achieved as 24 electrons rms, compared to spec of 25. • Comparator offset spread a few times larger than anticipated. Prototype 2 demonstrated: • All NMOS electronics without unacceptable power consumption • (not clear all NMOS electronics is a good alternative to deep P-well option) • Comparators offset calibration with virtually any required precision using analog calibration circuit. • Smaller feature size creates issues: sensor capacitance limits signal/noise ratio, stemming from 90 nm process design rules. CPAD Workshop, December 10, 2019, Madison Jim Brau 8
Prototype 3 - six sensor alternatives Six different sensor options were implemented on the same chip – 8 columns for each option: 1 Same as prototype 2 – for comparison. 1. 2 Deep NWELL diode in the window in P++ layer - design rules waiver. 2. Shallow NWELL diode, also in the window - design rules waiver. 3. 3 4. “Natural transistor” in the P++ layer window transistor is formed directly on P+ epi layer large source and drain diffusion areas gate connected to both source and drain and form sensor output. 4 5. Also “Natural transistor” but with 2 fingers source and drain are narrow 5&6 gate also connected to both, as in option 4. 6. Same as 5, however gate is not connected to source and drain, but connected to external bias voltage. CPAD Workshop, December 10, 2019, Madison Jim Brau 9
Deep NWELL (option 2) vs. shallow NWELL(option 3) Deep NWELL (option 2) larger area and larger charge collection efficiency, but larger capacitance. Shallow NWELL (option 3) smaller area, but P++ acts as charge reflector. Window size may define charge collection efficiency. CPAD Workshop, December 10, 2019, Madison Jim Brau 10
Options with “Natural transistor” Option 4 (1 finger) Larger nwells forming source and drain. Is charge collection efficiency better? What is impact of size on sensor capacitance? Option 5 (2 finger, gate to source and gain) Option 6 (2 finger, gate to external bias) How do these two options behave ? CPAD Workshop, December 10, 2019, Madison Jim Brau 11
Fe55 sensor capacitance test 𝐹 Fe55 1.6 ⋅ 10 − 19 𝐷 3.6 𝑓𝑊 𝐷 = 𝑊 max 𝐹 Fe55 = 5.9 keV diode option Capacitance (fF) μV/e 1 9.0 18 2 6.2 26 3 2.7 59 4 4.9 33 5 4.9 33 6 8.9 18 CPAD Workshop, December 10, 2019, Madison Jim Brau 12
Sensor noise measurements Option 3 Option 6 min Cap max Cap Option # Noise r.m.s (mV) Noise r.m.s (# electrons) 1 1.12 63 2 1.08 42 3 1.7 29 4 1.21 37 5 1.23 38 6 0.98 54 Noise larger, than expected from kTC noise formula. Additional noise pick up. CPAD Workshop, December 10, 2019, Madison Jim Brau 13
Noise observed vs expected Option sigma sigma Sqrt obs. exp. ( δ 2ob - δ 2ex ) (mV) (mV) (mV) Anomalous extra noise, 1 1.12 0.67 0.9 near pulse control 2 1.08 0.8 0.73 Max extra noise, min cap 3 1.7 1.21 1.2 4 1.21 0.9 0.8 5 1.23 0.9 0.84 6 0.98 0.67 0.72 Noise vs. Capacitance 1.3 Extra noise pick up 3 1.2 appears to occur mainly through 1.1 Noise (mV) 1 capacitive coupling to the sensor 1 0.9 0.8 0.7 0.6 0 2 4 6 8 10 Sensor Capacitance (fF) CPAD Workshop, December 10, 2019, Madison Jim Brau 14
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