Chapt er 13: Bit Level Arit hmet ic Archit ect ures Keshab K. - PowerPoint PPT Presentation

Chapt er 13: Bit Level Arit hmet ic Archit ect ures Keshab K. Parhi

• A W-bit f ixed point t wo’s complement number A is represent ed as : A=a w-1 .a w-2 … a 1 .a 0 where t he bit s ai, 0 ≤ i ≤ W-1, are eit her 0 or 1, and t he msb is t he sign bit . • The value of t his number is in t he range of [-1, 1 – 2 -W+1 ] and is given by : A = - a w-1 + Σ a w-1-i 2 -i • For bit -serial implement at ions, const ant word lengt h mult ipliers are considered. For a W × W bit mult iplicat ion t he W most -signif icant bit s of t he (2W-1 )-bit product are ret ained. Chap. 13 2

• Parallel Mult ipliers : − 1 W A = a w-1 .a w-2 … a 1 .a 0 = -a w-1 + ∑ a w-1-i 2 -i = i 1 − W 1 B = b w-1 .b w-2 … b 1 .b 0 = -b w-1 + ∑ b w-1-i 2 -i = 1 i Their product is given by : − 2 2 W p 2W-2-i 2 -i P = -p 2W-2 + ∑ = i 1 I n const ant word lengt h mult iplicat ion, W – 1 lower order bit s in t he product P are ignored and t he Product is denot ed as X ⇐ P = A × B, where − 1 W ∑ X = -x W-1 + x w-1-i 2 -i = i 1 Chap. 13 3

• P arallel Mult iplicat ion wit h Sign Ext ension : Using Horner’s rule, mult iplicat ion of A and B can be writ t en as = A × (-b W-1 + Σ b W-1-i 2 -i ) P = -A. b W-1 + [A. b W-2 + [A. b W-3 +[… + [A. b 1 + A b 0 2 -1 ] 2 - 1 ]… ]2 -1 ] 2 -1 where 2 -1 denot es scaling operat ion. • I n 2’s complement , negat ing a number is equivalent t o t aking it s 1’s complement and adding 1 t o lsb as shown below: − − = − W 1 − ∑ 2 i A a a − − − w 1 w 1 i = i 1 − − = + − − 1 1 W W − − ∑ ∑ ( 1 ) 2 i 2 i a a − − − w 1 w 1 i = = 1 1 i i − = + − − + W 1 − − + ∑ i W 1 a ( 1 a ) 2 1 2 − − − 1 1 w w i = i 1 − = − − + − + W 1 − − + ∑ i W 1 ( 1 a ) ( 1 a ) 2 2 − − − w 1 w 1 i = i 1 Chap. 13 4

Tabular f orm of bit -level array mult iplicat ion • The addit ions cannot be carried out direct ly due t o t erms having negat ive weight . Sign ext ension is used t o solve t his problem. For example, A = a 3 + a 2 2 -1 + a 1 2 -2 + a 0 2 -3 = -a 3 2 + a 3 + a 2 2 -1 + a 1 2 -2 + a 0 2 -3 = -a 3 2 2 + a 3 2 + a 3 + a 2 2 -1 + a 1 2 -2 + a 0 2 -3 describes sign ext ension of A by 1 and 2 bit s. Chap. 13 5

• Parallel Carry-Ripple Array Mult ipliers : Bit level dependence Graph Chap. 13 6

Parallel Carry Ripple Mult iplier Chap. 13 7

DG f or 4 × 4-bit carry save array mult iplicat ion P arallel carry-save array mult iplier Chap. 13 8

• Baugh-Wooley Mult ipliers: � Handles t he sign bit s of t he mult iplicand and mult iplier ef f icient ly. Tabular f orm of bit -level Baugh-Wooley mult iplicat ion Chap. 13 9

• P arallel Mult ipliers wit h Modif ied Boot h Recoding : � Reduces t he number of part ial product s t o accelerat e t he mult iplicat ion process. � The algorit hm is based on t he f act t hat f ewer part ial product s need t o be generat ed f or groups of consecut ive zeros and ones. For a group of “m” consecut ive ones in t he mult iplier, i.e., … 0{11… 1}0… = … 1{00… 0}0… - … 0{00… 1}0… = … 1{00… 1}0… inst ead of “m” part ial product s, only 2 part ial product s need t o be generat ed is signed digit represent at ion is used. � Hence, in t his mult iplicat ion scheme, t he mult iplier bit s are f irst recoded int o signed-digit represent at ion wit h f ewer number of nonzero digit s; t he part ial product s are t hen generat ed using t he recoded mult iplier digit s and accumulat ed. Chap. 13 10

b 2i+1 b 2i b 2i-1 b ’ Operat ion Comment s i 0 0 0 0 +0 st ring of 0’s 0 0 1 1 +A end of 1’s 0 1 0 1 +A a single 1 0 1 1 2 +2A end of 1’s 1 0 0 -2 -2A beginning of 1’s 1 0 1 -1 -A A single 0 1 1 0 -1 -A beginning of 1’s 1 1 1 0 -0 st ring of 1’s Radix-4 Modif ied Boot h Recoding Algorit hm Recoding operat ion can be described as: b ’ i = -2b 2i+1 + b 2i + b 2i-1 Chap. 13 11

I nterleaved Floor- Plan and Bit- Plane- Based Digital Filters • A const ant coef f icient FI R f ilt er is given by: y(n) = x(n) + f • x(n-1) + g • x(n-2) wher e, x(n) is t he input signal, and f and g ar e f ilt er coef f icient s. • The main idea behind t he int er leaved appr oach is t o per f or m t he comput at ion and accumulat ion of par t ial pr oduct s associat ed wit h f and g simult aneously t hus incr easing t he speed. • This incr eases t he accur acy as t r uncat ion is done at t he f inal st ep. • I f t he coef f icient s ar e int er leaved in such a way t hat t heir par t ial pr oduct s ar e comput ed in dif f er ent r ows, t he r esult ing ar chit ect ur e is called bit -plane ar chit ect ur e. Chap. 13 12

Bit- Serial Multipliers • Lyon’s Bit -Serial Mult iplier using Horner’s Rule : • For t he scaling operat or, t he f irst out put bit a 1 should be generat ed at t he same t ime inst ance when t he f irst input a 1 ent ers t he operat or. Since input a 1 has not ent ered t he syst em yet , t he scaling operat or is non-causal and cannot be implement ed in hardware. Chap. 13 13

Derivat ion of implement able bit -serial 2’s complement mult iplier Chap. 13 14

Lyon’s bit -serial 2’s complement mult iplier Chap. 13 15

Design of Bit- Serial Multipliers Using Systolic Mappings •Design of Lyon’s bit -serial mult iplier by syst olic mapping Using DG of ripple carry mult iplicat ion. p T e s T e e a(0,1) 1 1 Here, d T = [1 0], s T = [1 1] and b(1,0) 0 1 p T = [0 1] carry(1,0) 0 1 x(-1,1) 1 0 Chap. 13 16

•Design of bit -serial mult iplier by syst olic mapping using DG of ripple carry mult iplicat ion and t he f ollowing : d T = [0 1], s T = [0 1] and p T = [1 0] p T e s T e e a(0,1) 0 1 b(1,0) 1 0 carry(1,0) 1 0 x(-1,1) -1 1 Chap. 13 17

•Design of bit -serial mult iplier by syst olic mapping using DG f or carry-save array mult iplicat ion and t he f ollowing : d T = [1 0], s T = [1 1] and p T = [0 1] p T e s T e e a(0,1) 1 1 b(1,0) 1 1 carry(1,0) 0 1 x(-1,1) 1 0 Chap. 13 18

Dependence graph f or carry save Baugh-Wooley mult iplicat ion wit h carry ripple vect or merging Chap. 13 19

•Design of bit -serial Baugh-Wooley mult iplier by syst olic mapping using DG f or Baugh-Wooley mult iplicat ion and t he f ollowing : d T = [0 1], s T = [0 1] and p T = [1 0] p T e s T e e a(0,1) 0 1 carry(0,1) 0 1 b(1,0) 1 0 x(1,1) 1 1 carry-vm(-1,0) -1 0 Here, carry-vm denot es t he carry out put s in t he vect or merging port ion. Chap. 13 20

Bit -Serial Baugh-Wooley Mult iplier Chap. 13 21

DG bit -serial Baugh-Wooley mult iplier wit h carry-save array and vect or merging port ion t reat ed as t wo separat e planes Chap. 13 22

Bit -serial Baugh-Wooley mult iplier using t he DG having t wo separat e planes f or carry-save array and t he vect or merging port ion Chap. 13 23

Bit- Serial FI R Filter Bit -level pipelined bit -serial FI R f ilt er, y(n) = (-7/ 8)x(n) + (1/ 2)x(n-1), where const ant coef f icient mult iplicat ions are implement ed as shif t s and adds as y(n) = -x(n) + x(n)2 -3 + x(n-1)2 -1 . (a)Filt er archit ect ure wit h scaling operat ors; (b) f easible bit -level pipelined archit ect ure Chap. 13 24

Bit- Serial I I R Filter • Consider implement at ion of t he I I R f ilt er Y(n) = (-7/ 8)y(n-1) + (1/ 2)y(n-2) + x(n) where, signal word-lengt h is assumed t o be 8. • The f ilt er equat ion can be re-writ t en as f ollows: w(n) = (-7/ 8)y(n-1) + (1/ 2)y(n-2) Y(n) = w(n) + x(n) which can be implement ed as an FI R sect ion f rom y(n-1) wit h an addit ion and a f eedback loop as shown below: Chap. 13 25

• St eps f or deriving a bit -serial I I R f ilt er archit ect ure: � A bit -level pipelined bit -serial implement at ion of t he FI R sect ion needs t o be derived. � The input signal x(n) is added t o t he out put of t he bit - serial FI R sect ion w(n). � The result ing signal y(n) is connect ed t o t he signal y(n-1). � The number of delay element s in t he edge marked ?D needs t o be det ermined.(see f igure in next page) • For, syst ems cont aining loop, t he t ot al number of delay element s in t he loops should be consist ent wit h t he original SFG, in order t o maint ain synchronizat ion and correct f unct ionalit y. • Loop delay synchronization involves mat ching t he number of word-level loop delay element s and t hat in t he bit -serial archit ect ure. The number of bit -level delay element s in t he bit -serial loops should be W × N D , where W is signal word- lengt h and N D denot es t he number of delay element s in t he word-level SFG. Chap. 13 26

• Bit -level pipelined bit -serial archit ect ure, wit hout synchronizat ion delay element s. (b) Bit -serial I I R f ilt er. Not e t hat t his implement at ion requires a minimum f easible word-lengt h of 6. Chap. 13 27