Autumn VHDL course for TKK Digital design with Hardware Description - PowerPoint PPT Presentation

Autumn VHDL course for TKK Digital design with Hardware Description Languages Autumn 1999 Mikael Platan (mikael.platan@nokia.com) Mark Davidson (allan.davidson@nokia.com) Vesa Koskela (vesa.j.koskela@nokia.com) TKK S-88.133 autumn1999 Vko,MDa, 27.9.1999 OH 1

VHDL = VHSIC Hardware Description Language This course will cover two main topics: 1.) The VHDL language and it constraints. 2.) Why one would want to use the language in digital design. However, other questions will be answered such as • Where does it fit on the “world map” of hardware design? • Why is it here? • Why ever use VHDL? TKK S-88.133 autumn1999 Vko,MDa, 27.9.1999 OH 2

VHDL VHSIC Hardware Description Language VHSIC = Very High Speed Integrated Circuit TKK S-88.133 autumn1999 Vko,MDa, 27.9.1999 OH 3

Hardware Description Languages There are many HDLs with different features and goals: - VHDL : U.S. Department of Defense sponsored project (first standard 1987) Most wide spread in Europe - VERILOG : Proprietary language first then opened to the public (late 80’s) Most wide spread in the USA - UDL/I: Unified Design Language for IC:s. Developed in Japan for common interchange format between CAD tools. - SILAGE: Suited for DSP application. VHDL and VERILOG are the most common! TKK S-88.133 autumn1999 Vko,MDa, 27.9.1999 OH 4

VHDL History - Originated from the US Government VHSIC program A need was seen for a method in which to describe a digital circuit in such a manner that it was free from any technical constraints. This would allow the Department of Defense to replace an obsolete component with a new one without large amounts of re-design work. - Further developed by Institute of Electrical and Electronics Engineers (IEEE) - Adopted as an IEEE STANDARD1076 in 1987 Hence VHDL-87! - All IEEE standards are subject to a review every 5 years This is where VHDL-93 comes from! TKK S-88.133 autumn1999 Vko,MDa, 27.9.1999 OH 5

VHDL - language • IEEE standard hardware • For digital design/modeling Also a description language 1076-1987 AHDL (Analog HDL) is being VHDL-87 developed. This is due to the growing importance of mixed • Is based on the ADA language signal systems. • VHDL’s “worst” competitor is • Most important application is in VERILOG ASIC (Application Specific • New VHDL version was approved Integrated Circuit) design in 1993. VHDL-93 • It is used for modeling, simulation, • New VHDL version to be logic synthesis and testing approved early this year. It • Common method of modeling contains analog signal support. between designers and design tools TKK S-88.133 autumn1999 Vko,MDa, 27.9.1999 OH 6

VHDL features • Parallelisms. Different processes • Dynamic types and their use with can be active independently of e.g. attributes : each other. This is fundamentally FOR i IN j’range LOOP . .. an accurate model for a digital where the variable j’s range can system. dynamically changed. • Supports hierarchical design , top- • Overloading . E.g. the same down or bottom-up. function can be called with • Supports reuse through its different types of parameters. This library/package functions where is related to typing. To use the functions and components can be same function (operator) on collected different types of objects (operand) • Strongly typed language. This is one must define it multiply to be similar to Pascal and other compatible with all the required Software programming languages. types. It means that operands must be of the correct type for a operator to be called TKK S-88.133 autumn1999 Vko,MDa, 27.9.1999 OH 7

VHDL - world • Good overview from Internet: • Documents: “1076-1987 Standard http://vhdl.org VHDL Language Reference Manual”, “IEEE standard VHDL... • FAQ, Frequently Asked Questions, (-93)” in VHDL: http://vhdl.org/vi/comp.lang.vhdl/ • Numerous books: e.g. Perry - “VHDL”, Bhasker - “A VHDL • VHDL International organizations primer” e.g. standardization • Numerous VHDL products, also • Usenet news groups: some Public Domain. comp.lang.vhdl • The most known manufacturers: • Tutorials on the net, VHDL Synopsys, Mentor, Cadence, models, libraries, news etc Summit, Renoir, TransEDA • Many conferences. e.g. DAC • Design, Lecturing, Consulting, • http://www.mkp.com Subcontracting TKK S-88.133 autumn1999 Vko,MDa, 27.9.1999 OH 8

Modeling Digital Systems • Digital system = Any digital circuit that processes or stores information • These systems are complex: We need to recognize them as complex and have to find ways to deal with the complexity • The most important way is to adopt a systematic methodology of design • The term MODEL will refer to our understanding of a system. A model should allow us to make predictions about the system. • There can be several models of one system! TKK S-88.133 autumn1999 Vko,MDa, 27.9.1999 OH 9

Why MODELs 1) Formal model to communicate requirements. 2) Communicate and enhance the understanding of the function of a system 3) Models will allow testing and verification of a design using simulation. Thus allowing for the correction of errors before the system is manufactured. 4) Formal verification of the “correctness” of a design 5) To allow SYNTHESIS of circuits TKK S-88.133 autumn1999 Vko,MDa, 27.9.1999 OH 10

Why use Hardware Description Language for modeling • To model the design • To verify the model • To implement the model in hardware (synthesizing) • Using a language to do this allows for more levels of abstraction. Giving the designer more freedom to implement “ideas”, rather than specifics, results in higher quality designs in a shorter time. TKK S-88.133 autumn1999 Vko,MDa, 27.9.1999 OH 11

Remember! The idea behind all of these arguments is that: We want to achieve maximum reliability in the design process for a minimum cost and design time!! TKK S-88.133 autumn1999 Vko,MDa, 27.9.1999 OH 12

Domains and Levels of Modeling TKK S-88.133 autumn1999 Vko,MDa, 27.9.1999 OH 13

Functional At the most abstract level the system may be described in terms of ALGORITHMS NOTE! This is often called “BEHAVIOURAL MODELING” Example: loop for each data input loop read the value on this input; scale the value using the current scale factor for this input convert and write.... end loop; wait for 10ms; end loop; TKK S-88.133 autumn1999 Vko,MDa, 27.9.1999 OH 14

Structural The system may be described as an interconnection of components like processors, memories and i/o devices. Sometimes called as the Processor Memory Switch, PMS , level. Example: TKK S-88.133 autumn1999 Vko,MDa, 27.9.1999 OH 15

Geometric Top level abstraction: How the components described in the structural model are organized on the silicon die . Pad frame TKK S-88.133 autumn1999 Vko,MDa, 27.9.1999 OH 16

Next level in abstraction: REGISTER TRANSFER LEVEL Register Transfer Level: Structural model: Example: TKK S-88.133 autumn1999 Vko,MDa, 27.9.1999 OH 17

Register Transfer Language (RTL) In the functional domain a Register Transfer Language is used to specify the operation of a system at the Register Transfer Level: Example: MAR <- PC, memory_read <- 1 PC <- PC + 1 wait until ready = 1 IR <- memory_data memory_read <- 0 TKK S-88.133 autumn1999 Vko,MDa, 27.9.1999 OH 18

Most designers work more and more away from the center Tools help designers work away from the center TKK S-88.133 autumn1999 Vko,MDa, 27.9.1999 OH 19

Why VHDL as modeling language? • Includes facilities to describe structure and function at VARIOUS levels of abstraction (above gate level) • Has an attribute mechanism to annotate information from the geometric domain. • It can be used for specification, simulation and hardware synthesis • It is widely supported by CAD tool vendors. • It is a standard being continuously reviewed. TKK S-88.133 autumn1999 Vko,MDa, 27.9.1999 OH 20

Graphical Entry tools - need anymore to learn VHDL?! • Today many Graphical Entry tools that automatically generate VHDL code exist (Summit, Renoir) • They are becoming so good that they are already being used in production The need for writing actual code may have been reduced due to GE tools but: 1) the need to understand what was auto generated is still there 2) we still have to manage large amounts of vhdl blocks 3) VHDL is still the descriptive part 4) Many of the GE tools are not producing correct or optimized code in all situations. GE tools should be viewed as a complement not a replacement to VHDL. TKK S-88.133 autumn1999 Vko,MDa, 27.9.1999 OH 21

VHDL Modeling Concepts We have discussed three domains of modeling: 1) Function 2) Structure 3) Geometry We will now introduce VHDL elements to describe the basic modeling concept in each of the above 3 domains. NB: The objective is to GET A FEEL for VHDL as a description language - All these will be discussed in detail later. TKK S-88.133 autumn1999 Vko,MDa, 27.9.1999 OH 22

Entity TKK S-88.133 autumn1999 Vko,MDa, 27.9.1999 OH 23

Elements of Behavior - Internal function of an entity is called ARCHITECTURE - An architecture can have a number of alternative functions - A behavioral architecture of an entity consists of Process statements - Process statements are a collection of actions executed in sequence (sequential statements ) Example: TKK S-88.133 autumn1999 Vko,MDa, 27.9.1999 OH 24