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Authenticache: Harnessing Cache ECC for System Authentication Anys Bacha and Radu Teodorescu Department of Computer Science and Engineering The Ohio State University http://arch.cse.ohio-state.edu Security and Everyday Computing Security is

  1. Authenticache: Harnessing Cache ECC for System Authentication Anys Bacha and Radu Teodorescu Department of Computer Science and Engineering The Ohio State University http://arch.cse.ohio-state.edu

  2. Security and Everyday Computing Security is now crucial to all computing markets, especially with the advent of IoT 2 Authenticache: Harnessing Cache ECC for System Authentication Anys Bacha

  3. Security Challenges 3 Authenticache: Harnessing Cache ECC for System Authentication Anys Bacha

  4. Security Challenges • Password management • Complexity due to different accounts having policies 3 Authenticache: Harnessing Cache ECC for System Authentication Anys Bacha

  5. Security Challenges • Password management • Complexity due to different accounts having policies • Secure key storage • Increases complexity for low cost IoT devices 3 Authenticache: Harnessing Cache ECC for System Authentication Anys Bacha

  6. Security Challenges • Password management • Complexity due to different accounts having policies • Secure key storage • Increases complexity for low cost IoT devices • Software as a Service • Personal device at workplace increasing security risks 3 Authenticache: Harnessing Cache ECC for System Authentication Anys Bacha

  7. Physical Unclonable Functions (PUF) 4 Authenticache: Harnessing Cache ECC for System Authentication Anys Bacha

  8. Physical Unclonable Functions (PUF) Chip 5 Authenticache: Harnessing Cache ECC for System Authentication Anys Bacha

  9. Physical Unclonable Functions (PUF) Fast transistors Slow transistors Chip • Exploit randomness in silicon 5 Authenticache: Harnessing Cache ECC for System Authentication Anys Bacha

  10. Physical Unclonable Functions (PUF) Chip Silicon Fingerprints • Exploit randomness in silicon • Systematic outputs unique to device 6 Authenticache: Harnessing Cache ECC for System Authentication Anys Bacha

  11. PUF System Authentication 7 Authenticache: Harnessing Cache ECC for System Authentication Anys Bacha

  12. PUF System Authentication Enrollment Silicon Fingerprints 8 Authenticache: Harnessing Cache ECC for System Authentication Anys Bacha

  13. PUF System Authentication Enrollment … 00010 Silicon Fingerprints 8 Authenticache: Harnessing Cache ECC for System Authentication Anys Bacha

  14. PUF System Authentication Enrollment … 00010 11001 … Silicon Fingerprints 8 Authenticache: Harnessing Cache ECC for System Authentication Anys Bacha

  15. PUF System Authentication Enrollment … … Silicon Fingerprints Challenge Response 01100 00110 … … 00010 11001 9 Authenticache: Harnessing Cache ECC for System Authentication Anys Bacha

  16. PUF System Authentication Authentication Enrollment … … Challenge Response Response Challenge 01100 00110 01100 00110 … … … … 00010 11001 00010 11001 10 Authenticache: Harnessing Cache ECC for System Authentication Anys Bacha

  17. PUF System Authentication Authentication Enrollment … Auth. Request … Challenge Response Response Challenge 01100 00110 01100 00110 … … … … 00010 11001 00010 11001 10 Authenticache: Harnessing Cache ECC for System Authentication Anys Bacha

  18. PUF System Authentication Authentication Enrollment … … 01100 … Challenge Response Response Challenge 01100 00110 01100 00110 … … … … 00010 11001 00010 11001 11 Authenticache: Harnessing Cache ECC for System Authentication Anys Bacha

  19. PUF System Authentication Authentication Enrollment … … 01100 … 00110 … Challenge Response Response Challenge 01100 00110 01100 00110 … … … … 00010 11001 00010 11001 11 Authenticache: Harnessing Cache ECC for System Authentication Anys Bacha

  20. PUF System Authentication Authentication Enrollment … … 01100 … 00110 … Challenge Response Response Challenge 01100 00110 01100 00110 … … … … 00010 11001 00010 11001 11 Authenticache: Harnessing Cache ECC for System Authentication Anys Bacha

  21. Related Work 12 Authenticache: Harnessing Cache ECC for System Authentication Anys Bacha

  22. Related Work • Arbiter PUF (Lee et al. VLSI’04) • Signal traversing maze of cascaded switch blocks Aribiter PUF 12 Authenticache: Harnessing Cache ECC for System Authentication Anys Bacha

  23. Related Work • Arbiter PUF (Lee et al. VLSI’04) • Signal traversing maze of cascaded switch blocks Aribiter PUF • Ring Oscillator PUF (Suh et al. DAC’07) • Delay loops feeding oscillations into counters Ring Oscillator PUF 12 Authenticache: Harnessing Cache ECC for System Authentication Anys Bacha

  24. Related Work • Arbiter PUF (Lee et al. VLSI’04) • Signal traversing maze of cascaded switch blocks Aribiter PUF • Ring Oscillator PUF (Suh et al. DAC’07) • Delay loops feeding oscillations into counters Ring Oscillator PUF • SRAM PUF (Guajardo et al. CHES’07) • Power-on states of 6T SRAM cell SRAM PUF 12 Authenticache: Harnessing Cache ECC for System Authentication Anys Bacha

  25. Related Work • Arbiter PUF (Lee et al. VLSI’04) • Signal traversing maze of cascaded switch blocks Aribiter PUF • Ring Oscillator PUF (Suh et al. DAC’07) Authenticache: No custom hardware • Delay loops feeding oscillations into counters On-chip error correction logic in processor caches Ring Oscillator PUF • SRAM PUF (Guajardo et al. CHES’07) • Power-on states of 6T SRAM cell SRAM PUF 12 Authenticache: Harnessing Cache ECC for System Authentication Anys Bacha

  26. Cache Errors as Silicon Fingerprints 13 Authenticache: Harnessing Cache ECC for System Authentication Anys Bacha

  27. Cache Errors as Silicon Fingerprints • Caches optimized for density 14 Authenticache: Harnessing Cache ECC for System Authentication Anys Bacha

  28. Cache Errors as Silicon Fingerprints • Caches optimized for density • Sensitive to process variation 14 Authenticache: Harnessing Cache ECC for System Authentication Anys Bacha

  29. Cache Errors as Silicon Fingerprints • Caches optimized for density • Sensitive to process variation • Itanium processor 8 L2 caches Intel 9560 Processor 14 Authenticache: Harnessing Cache ECC for System Authentication Anys Bacha

  30. Cache Errors as Silicon Fingerprints • Caches optimized for density • Sensitive to process variation • Itanium processor 8 L2 caches Intel 9560 Processor 120 100 Cache Lines 80 60 40 20 0 0 -10 -20 -30 -40 -50 -60 Relative Correctable Error Range (mV) 15 Authenticache: Harnessing Cache ECC for System Authentication Anys Bacha

  31. Cache Errors as Silicon Fingerprints • Caches optimized for density • Sensitive to process variation • Itanium processor 8 L2 caches Intel 9560 Processor 120 100 Cache Lines 80 60 40 20 0 0 -10 -20 -30 -40 -50 -60 Relative Correctable Error Range (mV) 15 Authenticache: Harnessing Cache ECC for System Authentication Anys Bacha

  32. Cache Errors as Silicon Fingerprints • Caches optimized for density • Sensitive to process variation • Itanium processor 8 L2 caches Intel 9560 Processor 120 100 Cache Lines 80 60 40 20 0 0 -10 -20 -30 -40 -50 -60 Relative Correctable Error Range (mV) 15 Authenticache: Harnessing Cache ECC for System Authentication Anys Bacha

  33. Cache Errors as Silicon Fingerprints • Caches optimized for density • Sensitive to process variation • Itanium processor 8 L2 caches Intel 9560 Processor 120 100 Repeatable Cache Lines 80 60 40 20 0 0 -10 -20 -30 -40 -50 -60 Relative Correctable Error Range (mV) 15 Authenticache: Harnessing Cache ECC for System Authentication Anys Bacha

  34. Cache Errors as Silicon Fingerprints • Caches optimized for density • Sensitive to process variation • Itanium processor 8 L2 caches Intel 9560 Processor 120 100 L2 L2 L2 L2 Repeatable Cache Lines 80 60 L2 L2 L2 L2 40 20 0 0 -10 -20 -30 -40 -50 -60 Relative Correctable Error Range (mV) 15 Authenticache: Harnessing Cache ECC for System Authentication Anys Bacha

  35. Cache Errors as Silicon Fingerprints • Caches optimized for density • Sensitive to process variation • Itanium processor 8 L2 caches Intel 9560 Processor 120 5 100 L2 L2 L2 L2 Repeatable 4 Error Count Cache Lines 80 3 60 L2 L2 L2 L2 2 40 1 20 0 0 0 -10 -20 -30 -40 -50 -60 Relative Correctable Error Range (mV) Cache Line Address 16 Authenticache: Harnessing Cache ECC for System Authentication Anys Bacha

  36. Cache Errors as Silicon Fingerprints • Caches optimized for density • Sensitive to process variation • Itanium processor 8 L2 caches Intel 9560 Processor 120 5 100 Repeatable 4 Error Count Cache Lines 80 3 60 2 40 1 20 0 0 0 -10 -20 -30 -40 -50 -60 Relative Correctable Error Range (mV) Cache Line Address 16 Authenticache: Harnessing Cache ECC for System Authentication Anys Bacha

  37. Cache Errors as Silicon Fingerprints • Caches optimized for density • Sensitive to process variation • Itanium processor 8 L2 caches Intel 9560 Processor 120 5 100 Repeatable 4 Error Count Cache Lines 80 3 <1 overlap/cache 60 2 40 1 20 0 0 0 -10 -20 -30 -40 -50 -60 Relative Correctable Error Range (mV) Cache Line Address 17 Authenticache: Harnessing Cache ECC for System Authentication Anys Bacha

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