L09: Cache Name: ID: Question: Direct Mapping Cache Hit Rate - PowerPoint PPT Presentation

Jan 11, 2023 •542 likes •654 views

L09: Cache Name: ID: Question: Direct Mapping Cache Hit Rate Consider a 4-block empty Cache, and all blocks initially marked as not valid , Given the main memory word addresses 0 1 2 3 4 3 4 15, calculate Cache hit rate. Cache Index

L09: Cache Name: ID:
Question: Direct Mapping Cache Hit Rate Consider a 4-block empty Cache, and all blocks initially marked as not valid , Given the main memory word addresses “0 1 2 3 4 3 4 15”, calculate Cache hit rate. Cache Index Valid Tag Data 00 01 10 11
0 miss 1 miss 2 miss 3 miss 00 Mem(0) 00 Mem(0) 00 Mem(0) 00 Mem(0) 00 Mem(1) 00 Mem(1) 00 Mem(1) 00 Mem(2) 00 Mem(2) 00 Mem(3) miss 3 hit 4 hit 15 miss 4 01 4 00 Mem(0) 01 Mem(4) 01 Mem(4) 01 Mem(4) 00 Mem(1) 00 Mem(1) 00 Mem(1) 00 Mem(1) 00 Mem(2) 00 Mem(2) 00 Mem(2) 00 Mem(2) 00 Mem(3) 00 Mem(3) 00 Mem(3) 00 Mem(3) 11 15 ● 8 requests, 6 misses
Question: Multiword Direct Mapping Cache Hit Rate Consider a 2-block empty Cache, and each block is with 2-words. All blocks initially marked as not valid . Given the main memory word addresses “0 1 2 3 4 3 4 15”, calculate Cache hit rate. Cache Data Index Tag 00 01
0 miss hit miss 1 2 00 Mem(1) Mem(0) 00 Mem(1) Mem(0) 00 Mem(1) Mem(0) 00 Mem(3) Mem(2) 3 hit 4 miss 3 hit 01 5 4 00 Mem(1) Mem(0) 00 Mem(1) Mem(0) 01 Mem(5) Mem(4) 00 Mem(3) Mem(2) 00 Mem(3) Mem(2) 00 Mem(3) Mem(2) 4 hit 15 miss 01 Mem(5) Mem(4) 01 Mem(5) Mem(4) 11 15 14 00 Mem(3) Mem(2) 00 Mem(3) Mem(2) ● 8 requests, 4 misses
Question: Bit number in a Cache How many total bits are required for a direct mapped cache with 16KB of data and 4-word blocks assuming a 32-bit address?
Question: Bit number in a Cache How many total bits are required for a direct mapped cache with 16KB of data and 4-word blocks assuming a 32-bit address? Solution ◮ 16K bytes == 4K words == 1K blocks ◮ Tag field size = 32-(10+2+2) = 18 ◮ 2 10 × [ 4 × 32 + 18 + 1 ] = 2 10 × 147 = 147 Kbits
Question: Direct Mapping v.s. 2-Way Set Associate Consider the following two empty caches, calculate Cache hit rates for the reference word addresses: “0 4 0 4 0 4 0 4” Cache Cache Set Tag Data Index Valid Tag Data 0 00 1 01 0 10 1 11 (a) (b) (a) Direct Mapping; (b) 2-Way Set Associative.
Question: Direct Mapping v.s. 2-Way Set Associate Consider the following two empty caches, calculate Cache hit rates for the reference word addresses: “0 4 0 4 0 4 0 4” Cache Cache Set Tag Data Index Valid Tag Data 0 00 1 01 0 10 1 11 (a) (b) (a) Direct Mapping; (b) 2-Way Set Associative. ◮ Direct mapping: 0 hit (Ping pong effect) ◮ 2-Way Set Associative: 6 hits

Recommend

1 Classifying cache misses Cache Organization Classifying misses by causes (3Cs) Cache size,

Cache Performance Metrics Cache miss rate: number of cache misses divided by number of accesses Lecture 14: Hardware Approaches for Cache Optimizations Cache hit time: the time between sending address and data returning from cache Cache

608 views • 4 slides

Web Cache Consistency Web Cache Consistency Web Cache Consistency Web Cache Consistency

Web Cache Consistency Web Cache Consistency Web Cache Consistency Web Cache Consistency Requirements of performance, availability, and disconnected operation require us to relax the goal of semantic transparency. - HTTP 1.1 specification

598 views • 13 slides

What Is Memory Hierarchy A typical memory hierarchy today: Lecture 13: Cache Basics and Cache

What Is Memory Hierarchy A typical memory hierarchy today: Lecture 13: Cache Basics and Cache Performance Proc/Regs L1-Cache Bigger Faster L2-Cache Memory hierarchy concept, cache L3-Cache (optional) design fundamentals, set-associative

303 views • 4 slides

Cache Performance Associativity Replacement Samira Khan Cache Performance March 28,

3/28/17 Agenda Review from last lecture Cache access Cache Performance Associativity Replacement Samira Khan Cache Performance March 28, 2017 Direct-Mapped Cache: Placement and Access Cache Abstraction and Metrics 00 | 000

518 views • 16 slides

Plan Hierarchical memories and their impact on our programs 1 Cache Memories, Cache Complexity

Plan Hierarchical memories and their impact on our programs 1 Cache Memories, Cache Complexity Cache Analysis in Practice 2 Marc Moreno Maza The Ideal-Cache Model 3 University of Western Ontario, London, Ontario (Canada) Cache Complexity

632 views • 25 slides

Generations of Cache 1980: no cache in proc; 1989 first Intel proc with a cache on chip.

Generations of Cache 1980: no cache in proc; 1989 first Intel proc with a cache on chip. 1995 2-level cache on chip Instructions Per Cycle Lost to Memory 1st Alpha 340 ns/5.0 ns = 68 clks x 2 or 136 2nd Alpha 266 ns/3.3 ns

588 views • 46 slides

Caches Electronic Computers M Caches 1 Cache LOCALITY PRINCIPLE (SPATIAL AND TEMPORAL)

Caches Electronic Computers M Caches 1 Cache LOCALITY PRINCIPLE (SPATIAL AND TEMPORAL) WORKING SET CPU Cache Registers Cache I lev. Cache II lev. Cache III lev. Memory Disk Tape The cache is a memory with an access time some

572 views • 55 slides

1 Locate set Cache Read Example: Direct Mapped Cache (E = 1) Check if any line in set

Today Cache memory organization and operation Performance impact of caches Cache Memories The memory mountain Rearranging loops to improve spatial locality Using blocking to improve temporal locality CSci 2021: Machine

102 views • 8 slides

CSE378 - Cache Performance metrics for caches Parameters for cache design Basic performance

CSE378 - Cache Performance metrics for caches Parameters for cache design Basic performance metric: hit ratio h Goal: Have h as high as possible without paying too much for T cache h = Number of memory references that hit in the cache /

427 views • 6 slides

Memory Hierarchy: Cache Memory hierarchy Cache basics Locality Cache organization Cache-aware

Memory Hierarchy: Cache Memory hierarchy Cache basics Locality Cache organization Cache-aware programming How does execution time grow with SIZE? int[] array = new int[SIZE]; fillArrayRandomly(array); int s = 0; for (int i = 0; i <

848 views • 48 slides

Direct Map Cache and Set Associative Cache (Revision) Lecture 14 CDA 3103 07-07-2014 Example 1

Direct Map Cache and Set Associative Cache (Revision) Lecture 14 CDA 3103 07-07-2014 Example 1 A set-associative cache consists of 64 lines, or slots, divided into four-line sets. Main memory contains 4K blocks of 128 words each. Show the

357 views • 19 slides

Cache Creek Placer Area Fee Proposal History of Placer Mining at Cache Creek Prospecting in

Cache Creek Placer Area Fee Proposal History of Placer Mining at Cache Creek Prospecting in Colorado began in 1858 1859, First discovery of gold in Cache Creek Park 1860, Campbell and Shoewalter excavated their first pits in Cache

298 views • 13 slides

Cache Memory Chapter 17 S. Dandamudi Outline Introduction Types of cache misses

Cache Memory Chapter 17 S. Dandamudi Outline Introduction Types of cache misses How cache memory works Types of caches Why cache memory works Example implementations Cache design basics Pentium PowerPC

813 views • 28 slides

Cache Memory Chapter 17 S. Dandamudi Outline Introduction Types of cache misses

Cache Memory Chapter 17 S. Dandamudi Outline Introduction Types of cache misses How cache memory works Types of caches Why cache memory works Example implementations Pentium Cache design basics PowerPC

802 views • 56 slides

Cache Memories, Cache Complexity Marc Moreno Maza University of Western Ontario, London, Ontario

Cache Memories, Cache Complexity Marc Moreno Maza University of Western Ontario, London, Ontario (Canada) CS3101 and CS4402-9635 Plan Hierarchical memories and their impact on our programs Cache Analysis in Practice The Ideal-Cache Model

1.18k views • 100 slides

General Cache Mechanics CPU Block: unit of data in cache and memory. (a.k.a. line) Memory

General Cache Mechanics CPU Block: unit of data in cache and memory. (a.k.a. line) Memory Hierarchy: Cache Smaller, faster, more expensive. Cache 8 9 14 3 Stores subset of memory blocks . (lines) Data is moved in block units Memory

467 views • 8 slides

1 Trace Cache Summary of Reducing Cache Hit Time Trace: a dynamic sequence of Small and simple

Improving Cache Performance 1. Reducing miss rates 3. Reducing miss penalty or miss rates via parallelism Larger block size Lecture 18: Reducing Cache Hit Non-blocking caches larger cache size Time and Main Memory Design

285 views • 3 slides

Cache Performance Samira Khan March 28, 2017 Agenda Review from last lecture Cache

Cache Performance Samira Khan March 28, 2017 Agenda Review from last lecture Cache access Associativity Replacement Cache Performance Cache Abstraction and Metrics Address Tag Store Data Store (stores (is the address in

904 views • 61 slides

Cache Coherency and Memory Consistency Why On-Chip Cache Coherence is here to stay - Motivation:

Cache Coherency and Memory Consistency Why On-Chip Cache Coherence is here to stay - Motivation: There is skepticism about the scalability of cache coherence: Some argue: Availability of other paradigms such as message passing and

277 views • 13 slides

Lecture 21: Memory Hierarchy Todays topics: Cache organization Cache hits/misses 1

Lecture 21: Memory Hierarchy Todays topics: Cache organization Cache hits/misses 1 Cache Hierarchies Data and instructions are stored on DRAM chips DRAM is a technology that has high bit density, but relatively poor

419 views • 15 slides

mutexes / barriers / monitors 1 last time cache coherency multiple cores, each with own cache

mutexes / barriers / monitors 1 last time cache coherency multiple cores, each with own cache at most one cache with modifjed value watch other processors accesses to monitor value use invalidation to prevent others from getting modifjed

757 views • 75 slides

Cache Coherency Cache coherent processors most current value for an address is the last

Cache Coherency Cache coherent processors most current value for an address is the last write all reading processors must get the most current value Cache coherency problem update from a writing processor is not known to other

719 views • 30 slides

Chapter 4 Cache Memory Contents Computer memory system overview Characteristics of

Chapter 4 Cache Memory Contents Computer memory system overview Characteristics of memory systems Memory hierarchy Cache memory principles Elements of cache design Cache size Mapping function Replacement

793 views • 64 slides

Cache Digests for HTTP/2 Kazuho Oku Cache Digest (IETF 100) Pull Request #413 proposes:

Cache Digests for HTTP/2 Kazuho Oku Cache Digest (IETF 100) Pull Request #413 proposes: SENDING_CACHE_DIGEST SETTINGS Parameter switch to Cuckoo hashing thanks to Yoav Weiss for the proposal Cache Digest (IETF 100)

289 views • 6 slides