東工大理工 ATLAS 実験シリコン検出器アップグレード の為のテスト用 DAQ システム 計測システム研究会 @J-PARC 2014/11/20-21 廣瀬穣 for the ATLAS-Japan silicon group
Introduction • Inner detector in ATLAS ATLAS Detector ➡ Purpose : - Particle tracking - Vertexing ➡ Provides very important information for “every” reconstructed objects. ATLAS Inner Detector • ATLAS-Japan group is involved in the silicon tracker. ➡ Pixel detector ➡ SemiConductor Tracker (SCT) 2
Inner detector in HL-LHC ATLAS Pixel Detector LHC: L =1x10 34 cm -2 s -1 HL-LHC: L = 5x10 34 cm -2 s -1 ~year 2015 • Many problems to use the current design. ➡ Intolerable radiation damage - Fluence of ~10 16 n eq /cm 2 ➡ Unacceptable occupancy - 23 → 140 pp collisions in one bunch crossing. • Completely new design is under study for the upgrade. 3
Overview of the upgraded detector • Full silicon tracker. ➡ To have high granularity/fast responding detector. • Wide coverage of the detector acceptance. Concept ring+IBL ➡ Extend up to η <4.0. • Many studies are ongoing. ➡ Detector R&D, layout, support structure, cooling etc... New design (Not final) Current design TRT SCT SCT pixel pixel proton beam proton beam Center of the detector 4
Overview of the upgraded detector • Full silicon tracker. ➡ To have high granularity/fast responding detector. • Wide coverage of the detector acceptance. Concept ring+IBL ➡ Extend up to η <4.0. • Many studies are ongoing. ➡ Detector R&D, layout, support structure, cooling etc... New design (Not final) Current design ) ° 9 ~ ( 5 . 2 < | η | | η | < 4 . 0 ( ~ 2 ° ) proton beam proton beam Center of the detector 5
Overview of the upgraded detector • Full silicon tracker. ➡ To have high granularity/fast responding detector. Japanese group is working • Wide coverage of the detector acceptance. mainly on this part. Concept ring+IBL ➡ Extend up to η <4.0. • Many studies are ongoing. ➡ Detector R&D , layout, support structure, cooling etc... New design (Not final) Current design ) ° 9 ~ ( 5 . 2 < | η | | η | < 4 . 0 ( ~ 2 ° ) proton beam proton beam Center of the detector 6
Work field relating to DAQ • Pixel : ➡ DAQ development for testing new module design. • SCT : ➡ DAQ development for testing new module design. • Telescope to test the detectors above : ➡ DAQ development to readout telescopes. - Telescope : reference detector to provide hit position. ➡ Software to operate the telescope+DUT system. 7 ※ DUT : Device Under Test
Work field relating to DAQ • Pixel : ➡ DAQ development for testing new module design. • SCT : ➡ DAQ development for testing new module design. • Telescope to test the detectors above : ➡ DAQ development to readout telescopes. - Telescope : reference detector to provide hit position. ➡ Software to operate the telescope+DUT system. All these DAQ systems are developed based on the “SEABAS” board. 8 ※ DUT : Device Under Test
Introduction of the SEABAS board • SEABAS(2) : general purpose DAQ board with SiTCP . ➡ SiTCP : network processor to communicate with PC. Maximum data rate : 100 (1000) Mbps. ➡ FPGA for each user application. ➡ 2(4) × NIM_IN, 2 × NIM_OUT (trigger, busy etc...). ➡ 1(16)ch × ADC and 4ch × DAC Connectors for NIM I/O each application UserFPGA (120 signal lines from UserFPGA) Ethernet SiTCP (via TCP/UDP) ~ 20 cm 9
Advantage to use SEABAS • “Compact” and “versatile” DAQ system. ➡ Compact : - Don’t need large crates just for testing prototypes... ✓ E.g. NIM, CAMAC, VME, ATCA etc... - Portable system is preferable. ✓ We have to transport the system for the testbeam. ➡ Versatile : - Have to test new features of the prototype quickly. SEABAS is one of the good solution !! - enough data transfer speed. -enough I/O ports. 10
Pixel module readout 11
Upgrade of the pixel detector • Readout ASIC : FE-I3 → FE-I4. ➡ Smaller pixel size, faster readout speed. - To cope with higher hit rate. 20mm FE-I3 FE-I4 FE-I4 18 × 160 80 × 336 Pixel array 19mm Pixel size (um 2 ) 50 × 400 50 × 250 10.8mm Data rate 40 160 (Mb/s) FE-I3 CMOS 250 130 process (nm) 7.6mm 12
Expected module design • Final design for the pixel module uses an multiplexer (MUX). ➡ Since module mount have only two data line for one module. Module mount Data line A Data line B 13
Expected module design • Final design for the pixel module uses an multiplexer (MUX). ➡ Since module mount have only two data line for one module. Module mount FEI4 ① FEI4 ② Data line A Data line B FEI4 ③ FEI4 ④ 14
Expected module design • Final design for the pixel module uses an multiplexer (MUX). ➡ Since module mount have only two data line for one module. Module mount FEI4 ① FEI4 ② Data ① + ② MUX Data ③ + ④ MUX FEI4 ③ FEI4 ④ 15
FEI4-SEABAS2 DAQ system • Can readout up to four FEI4s ➡ MUX can be used to readout two FEI4s. 4-chip Control, adapter card analysis ... LAN SEABAS2 SCC × 4 FEI4 × 4 16
FEI4-SEABAS2 DAQ system • Can readout up to four FEI4s ➡ MUX can be used to readout two FEI4s. 4-chip Control, adapter card analysis ... LAN SEABAS2 MUX SCC × 4 FEI4 × 4 optional 17
Firmware design • To make flexible DAQ system ➡ Only provide the interface for ten FEI4 commands. - e.g. LV1Trigger, CalibrationPulse, WrRegister etc... ➡ All meaningful data from FEI4s is sent to PC. • All operation can be done by software coding. ➡ Relatively easy for non-DAQ expert to test new things. FEI4 × 4 SEABAS2 PC Command FEI4 SiTCP Com. 10b → 8b FIFO0 (RBCP) decoder Control FEI4 10b → 8b FIFO1 Analysis FEI4 SiTCP 10b → 8b FIFO2 (TCP) FEI4 FIFO3 10b → 8b Data 18
� � � � � � � � � 2 2 / ndf / ndf � � � � 5.685 / 8 5.685 / 8 (chip,col,row)=(0,34,11) Prob Prob 0.6825 0.6825 Threshold tuning 1.2 Threshold Threshold 2412 2412 ± ± 12.62 12.62 Hit efficiency Noise Noise 140.7 140.7 ± ± 21.83 21.83 1 Threshold 0.8 • To set same threshold among pixels. determination 0.6 ➡ Good example of the operation 0.4 for each pixel - Needs global configuration. 0.2 - Needs pixel local configuration. 0 0 5000 10000 - Charge injection Charge[e] - etc... Set global threshold 6 10 # pixels Mean:3596.3 0.8[e] ± Set local threshold 5 RMS :124.2[e] 10 Repeat 4 10 Charge injection × n After tuning 3 10 Before tuning Extract threshold 2 10 10 Save the best DAC value 1 0 2000 4000 6000 8000 10000 Threshold [e] 19
Strip module readout 20
Current/new design of the SCT module • Shorter strips to cope with high density of the particle. • Radiation hard ASIC and sensor. Current design New design 24 mm ABC250 R/O ASIC 120 mm (80 ASICs/module) ACBD R/O ASIC (12 ASICs/module) strip direction strip direction Hybrid (Unit of data structure) 768 strips 1280 strips 21
DAQ setup • Relatively large system : readout data from 16 modules. Detector ladder - 16 hybrids on top/bottom Hybrid - (Total 32 hybrids) Data from top/bottom side 16 16 Control, analysis ... Daughter board SEABAS 22
DAQ design 年憐 ⽉有 ⽇旦 日本物理学会 秋期大会 佐賀大学 システムの特徴 • SEABAS is purely used as an interface to pass... セットアップ ➡ “Command bit stream” from PC to each detector. からのコマンドビット列劣をそのままプロトタイプ検出器へ送る プロトタイプ検出器からの出⼒力曆ビット列劣を のタグ付けのみして へ送る ➡ “Hit data” with corresponding ID from detector to PC. 未加⼯左の出⼒力曆ビット列劣を直接 で確認可能なため、 デバッグが容易李 • Advantage : システム内でビット列劣の変換をしないため ➡ No firmware development is needed for future prototypes. 読み出し対象の仕様変更車に容易李に対応可能 PC SEABAS プロトタイプ検出器 コマンド … … … … SiTCP データ User FPGA Picture written by K. Todome 23
Example of the operation • Measuring the size of noise. • Procedure : ➡ Injecting a certain amount of charge. ➡ Repeat injection by changing the threshold setting. ➡ Fitting the efficiency curve by the error function. ➡ Extract parameter σ as the size of noise. %&' ���� ε hit [mV] !"# $%&' + = * 2√* / −& * 1& √- . (√* 3 ��� σ =noise �� ���� ���� ���� V threshold [mV] 24
Result of the noise measurement • Tried two ways to measure the noise. ➡ Measuring hybrid by hybrid. ➡ Measuring whole hybrids at the same time. Measuring at the same time Individual measurement ���� Noise [e] 800 Top side Bottom side 750 ? ���� 700 650 ���� Change to new one � 600 550 ���� 500 ��� �� �� ��� 0 2 4 6 8 10 12 14 16 �� ��� �� �� �� ��� Hybrid ID Hybrid ID Difference might be caused by the detector design. → Giving a feedback to designers. 25
Telescope development 26
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