Asynchronous system design flow based on Petri nets Microelectronics System Design Research Group School of Electrical, Electronic and Computer Engineering University of Newcastle upon Tyne DATE-2005 Asynchronous system design flow based on Petri nets – p.1/40
Outline Motivation BESST (BEhavioural Synthesis of Self-Timed Systems) design flow Splitting of control and data paths Synthesis of data path Adding security features to data path Direct mapping of control path from Labelled PNs Direct mapping of low-latency control path from STGs Logic synthesis of control path Summary Asynchronous system design flow based on Petri nets – p.2/40
Motivation: Asynchronous circuits Asynchronous circuits address International Technology Roadmap for Semiconductors (ITRS) challenges ITRS-2003: “As it becomes impossible to move signals across large die within one clock cycle or in a power-efficient manner, or to run control and dataflow processes at the same clock rate, the likely result is a shift to asynchronous design style.” Modularity and scalability (productivity and reuse) Low noise and electromagnetic emission (security) Robustness to parametric variations No clock skew Asynchronous system design flow based on Petri nets – p.3/40
Motivation: Petri nets Well developed theory Powerful modeling language Simple to understand Can be hidden from the designer (intermediate system representation in our design flow) p1 b p3 p2 c p4 a d p5 e p0 p8 i f p6 g p7 h Asynchronous system design flow based on Petri nets – p.4/40
Motivation: Petri nets Well developed theory Powerful modeling language Simple to understand Can be hidden from the designer (intermediate system representation in our design flow) p1 b p3 p2 c p4 a d p5 e p0 p8 i f p6 g p7 h Asynchronous system design flow based on Petri nets – p.4/40
Asynchronous design flows Syntax-driven translation (Tangram, Balsa) Computationally simple Local peephole optimisation Adopted by industry (Philips’ incubator company Handshake Solutions) Slow control circuit Logic synthesis (PipeFitter, TAST, MOODs, CASH) Separate synthesis and optimisation of control and data paths Adopted by industry (Theseus Logic (NCL)) Computationally hard for explicit logic synthesis Asynchronous system design flow based on Petri nets – p.5/40
BESST Design flow Input System Spec. Function Implementation Behavioural Verilog RTL Library Control/Data Splitting Testbench Deriviation VeriSyn manual Control Unit Synthesis Datapath Synthesis Simulation Control Path Spec. Data Path Spec. Testbench Labelled Petri Net Coloured Petri Net Behavioural Verilog Logic Synt. Direct Map. Coloured Petri Net Functional Timing Mapping ConfRes, PN2DCs, Simulation Simulation VeriSAT OptiMist PN2DCs, VeriMap System Timing Control Path Impl. Data Path Impl. Information Verilog Netlist Verilog Netlist Timing Extraction Control/Data Merging VeriSyn System Layout System Implementation Placement & Routing Verilog Netlist Conventional EDA tools Asynchronous system design flow based on Petri nets – p.6/40
Greatest Common Divisor (GCD) spec. 01 module gcd(x, y, z); 02 input [7:0] x, y; 03 output reg [7:0] z; 04 reg [7:0] x_reg, y_reg; 05 always 06 begin 07 x_reg = x; y_reg = y; 08 while (x_reg != y_reg) 09 begin 10 if (x_reg < y_reg) 11 y_reg = y_reg - x_reg; 12 else 13 x_reg = x_reg - y_reg; 14 end 15 z <= x_reg; 16 end 17 endmodule Asynchronous system design flow based on Petri nets – p.7/40
Splitting of control and data paths Input System Spec. Function Implementation Behavioural Verilog RTL Library Control/Data Splitting Testbench Deriviation VeriSyn manual Control Unit Synthesis Datapath Synthesis Simulation Control Path Spec. Data Path Spec. Testbench Labelled Petri Net Coloured Petri Net Behavioural Verilog Logic Synt. Direct Map. Coloured Petri Net Functional Timing Mapping ConfRes, PN2DCs, Simulation Simulation VeriSAT OptiMist PN2DCs, VeriMap System Timing Control Path Impl. Data Path Impl. Information Verilog Netlist Verilog Netlist Timing Extraction Control/Data Merging VeriSyn System Layout System Implementation Placement & Routing Verilog Netlist Conventional EDA tools Asynchronous system design flow based on Petri nets – p.8/40
Global PN for GCD Initial PN for GCD module always x_reg = x; y_reg = y; while (x_reg != y_reg) begin if (x_reg < y_reg) y_reg = y_reg - x_reg; else x_reg = x_reg - y_reg; end z <= x_reg; Asynchronous system design flow based on Petri nets – p.9/40
Global PN for GCD Always-statement refinement x_reg=x while z<=x_reg y_reg=y x_reg = x; y_reg = y; while (x_reg != y_reg) begin if (x_reg < y_reg) y_reg = y_reg - x_reg; else x_reg = x_reg - y_reg; end z <= x_reg; Asynchronous system design flow based on Petri nets – p.9/40
Global PN for GCD While-statement refinement x_reg=x x_reg!=y_reg if x_reg==y_reg z<=x_reg y_reg=y x_reg = x; y_reg = y; while (x_reg != y_reg) begin if (x_reg < y_reg) y_reg = y_reg - x_reg; else x_reg = x_reg - y_reg; end z <= x_reg; Asynchronous system design flow based on Petri nets – p.9/40
Global PN for GCD If-statement refinement x_reg=x x_reg>y_reg x_reg=x_reg−y_reg x ? y x_reg==y_reg z<=x_reg x_reg<y_reg y_reg=y_reg−x_reg y_reg=y x_reg = x; y_reg = y; while (x_reg != y_reg) begin if (x_reg < y_reg) y_reg = y_reg - x_reg; else x_reg = x_reg - y_reg; end z <= x_reg; Asynchronous system design flow based on Petri nets – p.9/40
Global PN for GCD Assignment-operation refinement px1 x px2 store_x gt pgt1 sub_gt pgt2 p0 cmp eq peq1 z dum0 dum1 cmp1 cmp2 lt plt1 sub_lt plt2 py1 y py2 store_y x_reg = x; y_reg = y; while (x_reg != y_reg) begin if (x_reg < y_reg) y_reg = y_reg - x_reg; else x_reg = x_reg - y_reg; end z <= x_reg; Asynchronous system design flow based on Petri nets – p.9/40
Syntax-driven translation # activate 1 ; 1 3 2 −> | x a[0..7] 1 2 1 2 1 2 −> − 1 1 1 2 1 2 −> /= do aux:a 2 1 2 ; 1 1 || −> −> z @0;1 2 2 ; 1 2 1 1 2 1 2 ; guard −> aux:b 1 2 2 1 −> 1 −> − 1 2 2 1 1 2 1 −> | y b[0..7] > 2 1 Asynchronous system design flow based on Petri nets – p.10/40
Labelled PN for GCD control path z_ack x_req store_x gt_ack gt pgt1 sub_gt pgt2 x_ack cmp_req z_req px1 px2 sub_gt_req p0 cmp1 cmp2 eq peq1 z x dum0 dum1 y cmp sub_lt_req py1 py2 eq_ack y_ack y_req store_y lt_ack lt plt1 sub_lt plt2 Asynchronous system design flow based on Petri nets – p.11/40
Coloured PN for GCD data path x_req x_mux x_ack x_cur x MUX_x_0 x−y MUX_x_1 REG_x SUB_gt CMP_xy x>y gt_ack x_store cmp_req cmp x=y eq_ack sub_gt_req sub_lt_req y_store x<y lt_ack SUB_lt REG_y y−x MUX_y_1 y MUX_y_0 y_cur y_req y_mux y_ack Asynchronous system design flow based on Petri nets – p.12/40
Control-data path interface z_ack z_req Control path sub_gt_req sub_lt_req cmp_req eq_ack gt_ack x_ack y_ack lt_ack x_req y_req x z y Data path Asynchronous system design flow based on Petri nets – p.13/40
Synthesis of data path Input System Spec. Function Implementation Behavioural Verilog RTL Library Control/Data Splitting Testbench Deriviation VeriSyn manual Control Unit Synthesis Datapath Synthesis Simulation Control Path Spec. Data Path Spec. Testbench Labelled Petri Net Coloured Petri Net Behavioural Verilog Logic Synt. Direct Map. Coloured Petri Net Functional Timing Mapping ConfRes, PN2DCs, Simulation Simulation VeriSAT OptiMist PN2DCs, VeriMap System Timing Control Path Impl. Data Path Impl. Information Verilog Netlist Verilog Netlist Timing Extraction Control/Data Merging VeriSyn System Layout System Implementation Placement & Routing Verilog Netlist Conventional EDA tools Asynchronous system design flow based on Petri nets – p.14/40
Coloured PN for GCD x_req x_mux x_ack x_cur x MUX_x_0 x−y MUX_x_1 REG_x SUB_gt CMP_xy x>y gt_ack x_store cmp_req cmp x=y eq_ack sub_gt_req sub_lt_req y_store x<y lt_ack SUB_lt REG_y y−x MUX_y_1 y MUX_y_0 y_cur y_req y_mux y_ack Asynchronous system design flow based on Petri nets – p.15/40
Mapping Coloured PN into circuit Register Operation Comparator Multiplexer req1 in1 in1 in1 ack ack Coloured PN gt_ack in out out out req eq_ack ack req req in2 in2 lt_ack in2 req2 req1 out in in1 in1 in1 out gt_ack out Circuit in2 in2 eq_ack REG OP CMP MUX ack in2 req ack req ack req lt_ack req2 Asynchronous system design flow based on Petri nets – p.16/40
GCD data path schematic x_store sub_gt_req MUX REG SUB x x_ack x x−y x_mux x_req gt_ack CMP z cmp_req eq_ack y ? x lt_ack y_req y_mux y y_ack MUX REG SUB sub_lt_req y y−x y_store Asynchronous system design flow based on Petri nets – p.17/40
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