ASPEN: A Scalable In- SRAM Architecture for Pushdown Automata - PowerPoint PPT Presentation

ASPEN: A Scalable In- SRAM Architecture for Pushdown Automata Kevin A Angstadt ∗ , Arun Subramaniyan ∗ , Elaheh Sadredini † , Reza Rahimi † , Kevin Skadron † , Westley Weimer ∗ , Reetuparna Das ∗ ∗ Computer Science and Engineering, University of Michigan † Department of Computer Science, University of Virginia This work is funded, in part, by the NSF (1763674, 1619098, CAREER-1652294 and CCF-1629450); Air Force (FA8750-17-2-0079); and CRISP, one of six centers in JUMP, a Semiconductor Research Corporation (SRC) program sponsored by DARPA.

Processing Growing Quantities of Data • 2.5 quintillion bytes of data/day • Analysis /manipulation requires deserializati tion • Most data use re recursi sively- nested g grammars • XML • JSON • Poor performance on CPU • High branching Source: Domo — Data Never Sleeps 5.0 2

<course> <footnote></footnote> <sln>10637</sln> <prefix>ACCTG</prefix> <crs>230</crs> <lab></lab> <sect>01</sect> <title>INT FIN ACCT</title> <credit>3.0</credit> <days>TU,TH</days> <times> <start>7:45</start> <end>9</end> </times> <place> <bldg>TODD</bldg> <room>230</room> </place> <instructor> B. MCELDOWNEY </instructor> <limit>0112</limit> <enrolled>0108</enrolled> </course> XML Nesting 3

<course> A <footnote></footnote> <sln>10637</sln> B C <prefix>ACCTG</prefix> <crs>230</crs> <lab></lab> C A C <sect>01</sect> <title>INT FIN ACCT</title> B C A A <credit>3.0</credit> <days>TU,TH</days> <times> B C <start>7:45</start> <end>9</end> B C </times> <place> A <bldg>TODD</bldg> <room>230</room> B C </place> <instructor> A B. MCELDOWNEY C A </instructor> <limit>0112</limit> B C <enrolled>0108</enrolled> </course> XML Nesting Subtree Mining 4

S <course> A <footnote></footnote> <sln>10637</sln> ⊣ Exp B C <prefix>ACCTG</prefix> <crs>230</crs> <lab></lab> C A C Term <sect>01</sect> <title>INT FIN ACCT</title> B C A A <credit>3.0</credit> Term int * <days>TU,TH</days> <times> B C <start>7:45</start> ( Exp <end>9</end> ) B C </times> <place> A <bldg>TODD</bldg> Term + Exp <room>230</room> B C </place> <instructor> Term int S → Exp ⊣ A B. MCELDOWNEY C A Exp → Term + Exp </instructor> ∣ Term <limit>0112</limit> B C int Term → int * Term <enrolled>0108</enrolled> ∣ ( Exp ) </course> ∣ int XML Nesting Subtree Mining Parsing 5

Processing Growing Quantities of Data • Automata/RegEx help tame analysis of big data sets • Frequent Itemset/Pattern Mining • NLP Part-of-Speech Tagging • Data Deduplication • Ensemble-Based Classification • Particle Physics Analyses • Growing number of architectural solutions Source: Domo — Data Never Sleeps 5.0 6

Automata/RegEx Processing Platforms Reconfigurable ial-Re Spatia Spa Existing A Architecture Custom A ASIC IC Neumann Von N 7

Automata/RegEx Processing Platforms REAPR PAP Reconfigurable Micron AP Cache Automaton ial-Re Spatia Spa Existing A Architecture Custom A ASIC IC Neumann VASim DFAGE HyperScan UAP iNFAnt2 Von N Becchi, et al. HARE PCRE IBM PowerEN 8

Automata/RegEx Processing Platforms REAPR PAP Reconfigurable Micron AP Cache Automaton ial-Re Spatia Spa Existing A Architecture Custom A ASIC IC CPU-Based Neumann VASim DFAGE HyperScan UAP iNFAnt2 Von N Becchi, et al. HARE PCRE IBM PowerEN 9

Automata/RegEx Processing Platforms REAPR PAP Reconfigurable Micron AP Cache Automaton ial-Re Spatia Spa Existing A Architecture Custom A ASIC IC GPU-Based CPU-Based Neumann VASim DFAGE HyperScan UAP iNFAnt2 Von N Becchi, et al. HARE PCRE IBM PowerEN 10

Automata/RegEx Processing Platforms REAPR PAP Reconfigurable Micron AP FPGA-Based Cache Automaton ial-Re Spatia Spa Existing A Architecture Custom A ASIC IC GPU-Based CPU-Based Neumann VASim DFAGE HyperScan UAP iNFAnt2 Von N Becchi, et al. HARE PCRE IBM PowerEN 11

Automata/RegEx Processing Platforms REAPR PAP Reconfigurable Micron AP FPGA-Based Cache Automaton Finite automata are fu limited in the kinds fundam amental ally li and complexity of analyses they support ial-Re Spatia Spa PEN is a new processor—inspired by automata ASPE Existing A Architecture Custom A ASIC IC GPU-Based CPU-Based processing—that supports a richer c computational m model Neumann VASim DFAGE HyperScan UAP iNFAnt2 Von N Becchi, et al. HARE PCRE IBM PowerEN 12

Automata/RegEx Processing Platforms REAPR PAP Reconfigurable Micron AP FPGA-Based Cache Automaton Finite automata are fu limited in the kinds fundam amental ally li and complexity of analyses they support ial-Re Spatia Spa PEN is a new processor—inspired by automata ASPE Existing A Architecture Custom A ASIC IC GPU-Based CPU-Based processing—that supports a richer c computational m model Neumann VASim DFAGE HyperScan UAP iNFAnt2 Von N Becchi, et al. HARE PCRE IBM PowerEN 13

ASPEN Supports Richer Analyses • A ccelerated in- S RAM P ushdown EN EN gine • Scalable processing engine that uses L LLC s slices to accelerate Pushdown Automata computation • Custom five-stage datapath using SRAM lookups can process up to on one by byte per c cycle • Optimizing compiler supports ts e existi ting gra grammars , packs states efficiently, and reduces the number processing stalls • Provides additional cache when not in use 14

Overview of this Talk • Pushdown Automata Refresher • Architectural Design of ASPEN • Why LLC? • Datapath innovation • Optimizations • Evaluation • XML Parsing • Subtree Mining Source: https://www.flickr.com/photos/10623456@N02/45022262771 CC BY-NC 2.0 15

STACK ST ⊥ 0 0 * 0 Pop 0 Pop 1 Push ‘0’ No Push c ε * ⊥ Pop 0 Pop 0 No Push No Push 1 1 * 1 Pop 0 Pop 1 Push ‘1’ No Push Pushdown Automata Refresher 16

ST STACK ⊥ 0 0 * 0 Pop 0 Pop 1 Push ‘0’ No Push c ε * ⊥ Pop 0 Pop 0 No Push No Push 1 1 * 1 Pop 0 Pop 1 Push ‘1’ No Push Finite State Control Pushdown Automata Refresher 17

STACK ST ⊥ 0 0 * 0 Pop 0 Pop 1 Push ‘0’ No Push c ε * ⊥ Stack Memory Pop 0 Pop 0 No Push No Push 1 1 * 1 Pop 0 Pop 1 Push ‘1’ No Push Finite State Control Pushdown Automata Refresher 18

STACK ST ⊥ Input Symbol Match 0 0 * 0 Pop 0 Pop 1 Push ‘0’ No Push c ε * ⊥ Stack Memory Pop 0 Pop 0 No Push No Push 1 1 * 1 Pop 0 Pop 1 Push ‘1’ No Push Finite State Control Pushdown Automata Refresher 19

STACK ST ⊥ Input Symbol Match 0 0 * 0 Pop 0 Pop 1 Top of Stack Match Push ‘0’ No Push c ε * ⊥ Stack Memory Pop 0 Pop 0 No Push No Push 1 1 * 1 Pop 0 Pop 1 Push ‘1’ No Push Finite State Control Pushdown Automata Refresher 20

STACK ST ⊥ Input Symbol Match 0 0 * 0 Pop 0 Pop 1 Top of Stack Match Push ‘0’ No Push c ε * ⊥ Stack Memory Stack Actions Pop 0 Pop 0 No Push No Push 1 1 * 1 Pop 0 Pop 1 Push ‘1’ No Push Finite State Control Pushdown Automata Refresher 21

STACK ST ⊥ Input Symbol Match 0 0 * 0 Pop 0 Pop 1 Top of Stack Match Push ‘0’ No Push c ε Deterministic Pushdown Automata (DPDA) av avoid * ⊥ Stack Memory Stack Actions Pop 0 Pop 0 stack d divergence , but still support parsing of most No Push No Push 1 1 * common languages 1 Pop 0 Pop 1 Push ‘1’ No Push Finite State Control Pushdown Automata Refresher 22

Recognizing Palindromes with a Middle Character STACK ST ⊥ 0 0 * 0 Pop 0 Pop 1 Push ‘0’ No Push c ε * ⊥ Pop 0 Pop 0 No Push No Push 1 1 * 1 Pop 0 Pop 1 Push ‘1’ No Push 01010c0 c01010 23

Recognizing Palindromes with a Middle Character STACK ST ⊥ 0 0 * 0 Pop 0 Pop 1 Push ‘0’ No Push c ε * ⊥ Pop 0 Pop 0 No Push No Push 1 1 * 1 Pop 0 Pop 1 Push ‘1’ No Push 01010c0 c01010 24

Recognizing Palindromes with a Middle Character STACK ST 0 0 0 * 0 ⊥ Pop 0 Pop 1 Push ‘0’ No Push c ε * ⊥ Pop 0 Pop 0 No Push No Push 1 1 * 1 Pop 0 Pop 1 Push ‘1’ No Push 010 1010 10c010 1010 10 25

Recognizing Palindromes with a Middle Character STACK ST 1 0 0 * 0 0 Pop 0 Pop 1 Push ‘0’ No Push c ε ⊥ * ⊥ Pop 0 Pop 0 No Push No Push 1 1 * 1 Pop 0 Pop 1 Push ‘1’ No Push 01010c0 c01010 26

Recognizing Palindromes with a Middle Character STACK ST 0 0 0 * 0 1 Pop 0 Pop 1 Push ‘0’ No Push c ε 0 * ⊥ Pop 0 Pop 0 No Push No Push 1 1 ⊥ * 1 Pop 0 Pop 1 Push ‘1’ No Push 01010 01 10c010 1010 10 27