Apps with Hardware: Enabling Run-time Architectural Customization in Smart Phones Michael Coughlin, Ali Ismail, and Eric Keller, University of Colorado, Boulder https://www.usenix.org/conference/atc16/technical-sessions/presentation/coughlin This paper is included in the Proceedings of the 2016 USENIX Annual Technical Conference (USENIX ATC ’16). June 22–24, 2016 • Denver, CO, USA 978-1-931971-30-0 Open access to the Proceedings of the 2016 USENIX Annual Technical Conference (USENIX ATC ’16) is sponsored by USENIX.
Apps with Hardware: Enabling Run-time Architectural Customization in Smart Phones Michael Coughlin , Ali Ismail , Eric Keller University of Colorado, Boulder Abstract In this paper we present a novel system which incorpo- rates programmable hardware (an FPGA) into a smart App App phone to enable a vision where apps can include both software and hardware components, or apps with hard- HW SW HW SW ware. We introduce a novel mechanism to enable sharing the FPGA in a practical manner by leveraging the unique deployment model of mobile applications - namely that Android deployment is via an app store, where we introduce a new cloud-based compilation. We present our proto- type smart phone using the Zedboard, which pairs a Xil- inx Zynq FPGA with an embedded Cortex A9, running FPGA ARM an Android-based system which we extended to pro- vide run-time system support for dynamically managing apps with hardware and providing a secure loading sys- tem. With this prototype, our evaluation demonstrates Figure 1: Smart phone with a processor (ARM) coupled the performance gains for an AES encryption module with programmable hardware (FPGA). (representing cryptography), a QAM modulation mod- users and application developers? ule (representing software-defined radio) of 3x to several In this paper, we present our ‘apps with hardware’ vi- orders of magnitude, with room for improvement and a sion (illustrated in Figure 1), design, and implementa- hardware-based memory scanner (representing custom tion which incorporates programmable hardware, such co-processors). We demonstrate the feasibility of our as an FPGA (field programmable gate array), into a smart cloud-based compilation within the context of real app phone 1 , and extends a mobile operating system to allow store statistics. Finally, we present a case study of a com- for application control of the current hardware configura- plete integration of hardware into an existing application tion ( e.g., by including the hardware configuration with (the Orbot Tor client). their app). The high-level idea is to couple software-like (re)programmability with hardware-like performance. In 1 Introduction providing programmability, the phone vendor empow- ers the application developers (and by extension the end users) with the ability to influence the design decisions. In designing new smart phone devices, the vendor must Developers, for example, would be able to introduce operate under a number of constraints – form factor, functionality, cost, energy use, etc. This leads to the ven- 1 We envision this as being commercially available smart phones, dor making a number of decisions regarding the various not just in prototyping devices – a vision supported by the commercial tradeoffs. These decisions, however, can then lead to the availability of system-on-chip devices which already couple an ARM processor that is widely used in smart phones (such as the ARM Cortex case where the device has both too little (the application A9 processor found in the iPhone 4) with reconfigurable logic [5, 25], developers/users want more) and too much (the applica- with or more recently the ARM Cortex A53 [26], and further supported tion developers/users don’t use what is there). What if by recent advances by vendors where hardware modules can be de- there was a way to put these trade-offs into the hands of signed using a high-level language, such as C++ [23]. USENIX Association 2016 USENIX Annual Technical Conference 621
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