Application of CADP to Hardware Validation Abderahman KRIOUILE and - PowerPoint PPT Presentation

Application of CADP to Hardware Validation Abderahman KRIOUILE and Massimo ZENDRI STMicroelectronics Forum Méthodes Formelles "Le Model-Checking en action" Toulouse, France, Oct 2014

Agenda 2 • 20 years of Hardware Validation with CADP • Presentation of hardware case studies • Four Types of Studies • Formal Modeling • Functional Verification • Model-based Testing • Performance Evaluation • Conclusion Application of CADP to Hardware Validation 15/10/2014

20 Years of Hardware Validation with CADP 3 1995 2000 2005 2010 2015 Application of CADP to Hardware Validation 15/10/2014

20 Years of Hardware Validation with CADP 4 High-level NovaScale/FAME Supercomputers FAME2 Polykid SCSI-2 Multiprocessor xSTream AMBA ACE SoC CC-NUMA Powerscale Platform2012 Blitter Display On-Chip level STBus SoC Utah NoC 2D Mesh NoC DES Asynchronous logic FAUST/MAGALI Low-level 1995 2000 2005 2010 2015 Application of CADP to Hardware Validation 15/10/2014

20 Years of Hardware Validation with CADP 5 High-level NovaScale/FAME Powerscale Supercomputers FAME2 Polykid • multiprocessor architecture SCSI-2 based on PowerPC microprocessors Multiprocessor xSTream AMBA ACE SoC CC-NUMA used in Bull’s Escala Powerscale Platform2012 servers and Blitter Display On-Chip level workstations STBus SoC Utah NoC 2D Mesh NoC DES Asynchronous logic FAUST/MAGALI Low-level 1995 2000 2005 2010 2015 Application of CADP to Hardware Validation 15/10/2014

20 Years of Hardware Validation with CADP 6 High-level NovaScale/FAME Polykid Supercomputers FAME2 Polykid • multiprocessor architecture SCSI-2 based on PowerPC • CC-NUMA memory model Multiprocessor xSTream AMBA ACE SoC CC-NUMA • 2 cache coherency levels Powerscale Platform2012 Blitter Display On-Chip level STBus SoC Utah NoC 2D Mesh NoC DES Asynchronous logic FAUST/MAGALI Low-level 1995 2000 2005 2010 2015 Application of CADP to Hardware Validation 15/10/2014

20 Years of Hardware Validation with CADP 7 High-level NovaScale/FAME SCSI-2 Supercomputers FAME2 Polykid • SCSI-2 bus arbitration SCSI-2 protocol • bus grant based on fixed Multiprocessor xSTream AMBA ACE SoC CC-NUMA priorities (SCSI numbers) Powerscale Platform2012 • unexpected OS deadlocks reported by Bull Blitter Display On-Chip level STBus SoC Utah NoC 2D Mesh NoC DES Asynchronous logic FAUST/MAGALI Low-level 1995 2000 2005 2010 2015 Application of CADP to Hardware Validation 15/10/2014

20 Years of Hardware Validation with CADP 8 High-level NovaScale/FAME NovaScale/FAME Supercomputers FAME2 Polykid • 64-bit high-end servers SCSI-2 based on Intel's Itanium-2 Multiprocessor xSTream AMBA ACE SoC • CC-NUMA CC-NUMA architecture Powerscale Platform2012 • focus on most critical, asynchronous parts Blitter Display On-Chip level STBus SoC Utah NoC 2D Mesh NoC DES Asynchronous logic FAUST/MAGALI Low-level 1995 2000 2005 2010 2015 Application of CADP to Hardware Validation 15/10/2014

20 Years of Hardware Validation with CADP 9 High-level NovaScale/FAME STBus SoC Supercomputers FAME2 Polykid • STBus interconnect protocol SCSI-2 • dedicated to high bandwidth Multiprocessor xSTream AMBA ACE SoC SoCs CC-NUMA Powerscale Platform2012 • audio-video processing Blitter Display On-Chip level STBus SoC Utah NoC 2D Mesh NoC DES Asynchronous logic FAUST/MAGALI Low-level 1995 2000 2005 2010 2015 Application of CADP to Hardware Validation 15/10/2014

20 Years of Hardware Validation with CADP 10 High-level NovaScale/FAME FAME 2 Supercomputers FAME2 Polykid • multiprocessor architectures SCSI-2 • CC-DSM: cache coherent- distributed shared memory Multiprocessor xSTream AMBA ACE SoC CC-NUMA • MPI benchmark: ping-pong Powerscale Platform2012 protocol • performance Blitter Display On-Chip level prediction STBus SoC Utah NoC 2D Mesh NoC DES Asynchronous logic FAUST/MAGALI Low-level 1995 2000 2005 2010 2015 Application of CADP to Hardware Validation 15/10/2014

20 Years of Hardware Validation with CADP 11 High-level NovaScale/FAME DES Supercomputers FAME2 Polykid SCSI-2 • Data Encryption Standard • asynchronous circuit Multiprocessor xSTream AMBA ACE SoC CC-NUMA • no clock: gates evolve Powerscale Platform2012 concurrently and synchronize via handshake protocols Blitter Display On-Chip level • no constraints on STBus SoC Utah NoC communication 2D Mesh NoC delays DES Asynchronous logic FAUST/MAGALI Low-level 1995 2000 2005 2010 2015 Application of CADP to Hardware Validation 15/10/2014

20 Years of Hardware Validation with CADP 12 High-level NovaScale/FAME FAUST/MAGALI Supercomputers FAME2 Polykid • GALS architecture SCSI-2 • asynchronous NoC • CHP (communi- Multiprocessor xSTream AMBA ACE SoC CC-NUMA cating Hardware Powerscale Platform2012 Processes) model Blitter Display On-Chip level STBus SoC Utah NoC 2D Mesh NoC DES Asynchronous logic FAUST/MAGALI Low-level 1995 2000 2005 2010 2015 Application of CADP to Hardware Validation 15/10/2014

20 Years of Hardware Validation with CADP 13 High-level NovaScale/FAME xSTream Supercomputers • multiprocessor FAME2 Polykid dataflow architecture SCSI-2 • high performance embedded Multiprocessor xSTream AMBA ACE SoC multimedia streaming CC-NUMA Powerscale Platform2012 applications • expected Performance Blitter Display On-Chip level measures: STBus SoC • latency Utah NoC • throughput 2D Mesh NoC DES • resource utilization Asynchronous logic FAUST/MAGALI Low-level 1995 2000 2005 2010 2015 Application of CADP to Hardware Validation 15/10/2014

20 Years of Hardware Validation with CADP 14 High-level NovaScale/FAME Blitter Display Supercomputers FAME2 • MULTIVAL project Polykid • 2D graphics co-processor SCSI-2 implementing BLIT (Block Multiprocessor xSTream AMBA ACE SoC CC-NUMA Image Transfer) and numerous Powerscale Platform2012 graphical operators • SystemC/TLM model Blitter Display On-Chip level STBus SoC Utah NoC 2D Mesh NoC DES Asynchronous logic FAUST/MAGALI Low-level 1995 2000 2005 2010 2015 Application of CADP to Hardware Validation 15/10/2014

20 Years of Hardware Validation with CADP 15 High-level NovaScale/FAME 2D Mesh NoC Supercomputers FAME2 Polykid • 5x5 2D-mesh NoC SCSI-2 • predict mean latency of Multiprocessor xSTream AMBA ACE SoC end-to-end communication CC-NUMA Powerscale Platform2012 Blitter Display On-Chip level STBus SoC Utah NoC 2D Mesh NoC DES Asynchronous logic FAUST/MAGALI Low-level 1995 2000 2005 2010 2015 Application of CADP to Hardware Validation 15/10/2014

20 Years of Hardware Validation with CADP 16 High-level NovaScale/FAME Platform2012 DTD Supercomputers FAME2 Polykid • Dynamic Task Dispatcher SCSI-2 • tasks divided in concurrently Multiprocessor xSTream AMBA ACE SoC executable sub-tasks (same CC-NUMA Powerscale Platform2012 code, different data) • dedicated hardware to switch Blitter Display On-Chip level tasks in only few clock cycles STBus SoC Utah NoC 2D Mesh NoC DES Asynchronous logic FAUST/MAGALI Low-level 1995 2000 2005 2010 2015 Application of CADP to Hardware Validation 15/10/2014

20 Years of Hardware Validation with CADP 17 High-level NovaScale/FAME Utah NoC Supercomputers FAME2 Polykid • two-dimensional mesh SCSI-2 • routing algorithm tolerating Multiprocessor xSTream AMBA ACE SoC link faults CC-NUMA Powerscale • Platform2012 check absence of deadlocks Blitter Display On-Chip level STBus SoC Utah NoC 2D Mesh NoC DES Asynchronous logic FAUST/MAGALI Low-level 1995 2000 2005 2010 2015 Application of CADP to Hardware Validation 15/10/2014

20 Years of Hardware Validation with CADP 18 High-level NovaScale/FAME AMBA ACE SoC Supercomputers FAME2 • heterogeneous SoC Polykid • ACE protocol: system level SCSI-2 cache coherency standard Multiprocessor xSTream AMBA ACE SoC • support for ARM@Big.LITTLE TM CC-NUMA Powerscale Platform2012 • integrated to STMicro set top box SoC for multiple Ultra HD Blitter Display On-Chip level STBus SoC Utah NoC 2D Mesh NoC DES Asynchronous logic FAUST/MAGALI Low-level 1995 2000 2005 2010 2015 Application of CADP to Hardware Validation 15/10/2014

Four Types of Studies 19 • Formal Modeling • Functional Verification • Model-based Testing • Performance Evaluation Application of CADP to Hardware Validation 15/10/2014

Formal Modeling 20 • Modeling languages used in these case studies • Before 2008-2009: LOTOS • Since then: LNT • LOTOS vs LNT • Both are formal languages to describe asynchronously-concurrent systems • LNT more convenient for human users • LNT closer to programing languages and hardware languages (such as VHDL) • Starting point for producing formal models: • Natural language descriptions (English text, tables, diagrams) • Programs in other hardware languages (CHP, SystemC/TLM, etc.) • Guidelines must be followed when developing formal models: • Focus on complex parts of the system (parallelism, concurrency, etc.) • Use abstractions to hide irrelevant details Application of CADP to Hardware Validation 15/10/2014