Analysis and Optimization of Analysis and Optimization of Thermal Issues in High Thermal Issues in High Performance VLSI Performance VLSI Kaustav Banerjee Stanford University Massoud Pedram and Amir H. Ajami University of Southern California ISPD 2001 ISPD 2001 K. Banerjee, M. Pedram and A. H. Ajami
Presentation Outline Presentation Outline � Introduction � Thermal Effects and Reliability � Interconnect Performance Optimization � High-Current Effects: ESD � Analysis of Non-uniform Chip Temperature � Non- Uniform Temperature Dependent Delay � Circuit Optimization: Clock Skew � Summary ISPD 2001 ISPD 2001 K. Banerjee, M. Pedram and A. H. Ajami
Introduction Introduction � Sources of chip power dissipation � Chip temperature model � Thermal effects in interconnects � Scaling trends and implications ISPD 2001 ISPD 2001 K. Banerjee, M. Pedram and A. H. Ajami
Sources of Chip Power Dissipation Sources of Chip Power Dissipation Devices: Close to Heat Sink Devices: Close to Heat Sink � Dynamic Power: ∝ ∝ ∝ ∝ CV 2 f most significant � Dynamic Power: ∝ ∝ ∝ ∝ CV 2 f most significant � Leakage Power: increasing with scaling � Leakage Power: increasing with scaling � C dominated by interconnects � C dominated by interconnects � Affects interconnect temperature � Affects interconnect temperature Interconnects: Away from Heat Sink Interconnects: Away from Heat Sink � Joule Heating: I 2 R � Joule Heating: I 2 R ISPD 2001 ISPD 2001 K. Banerjee, M. Pedram and A. H. Ajami
Chip Temperature Model Chip Temperature Model P/A ● 1-D Heat Conduction T Die P = = = = + + + + � � � � � � � � T T R Die O n � � � � � � � � A � � � � � � � � ● T Die = 120 °C (180 nm Node) Si Substrate ● R n = 4.75 cm 2 °C/W R n ● Assuming same Packaging Package and Cooling Technologies (Same R n ) Heat Sink T Die at Other Technology T O = 25 °C Nodes Calculated ISPD 2001 ISPD 2001 K. Banerjee, M. Pedram and A. H. Ajami
Thermal Effects in Interconnects Thermal Effects in Interconnects � An inseparable aspect of electrical power distribution and signal transmission through the interconnects � Arise due to self-heating (or Joule heating) of interconnects caused by current flow � Thermal effects impact interconnect electromigration reliability and design ISPD 2001 ISPD 2001 K. Banerjee, M. Pedram and A. H. Ajami
Thermal Effects in Interconnects Thermal Effects in Interconnects Self Heating under DC Stress (IRPS 96) Cross section 600 M3 Thickness of AlCu in M4 is doubled M1 500 M4 400 AlCu TiN ∆ T [ 0 C] M2 300 M1: Metal1 θ θ θ θ j t ox ∆ ∆ ∆ 200 M2: Metal2 increasing Oxide = 1000 µ µ µ µ L m t ox M3: Metal3 100 W = = = µ µ µ µ 3 m M4: Metal4 0 Silicon 0 1 2 3 4 Thermal impedance θ θ j , θ θ Power [W] defined by ∆ ∆ ∆ T = P x θ ∆ θ j θ θ � ∆ ∆ T increases with increasing t ox ∆ ∆ ISPD 2001 ISPD 2001 K. Banerjee, M. Pedram and A. H. Ajami
Thermal Effects in Interconnects Thermal Effects in Interconnects Impact of Scaling Using Low-k ( IEDM 96 ) DC Conditions Metal Metal Low-K (Gap Fill) SiO 2 SiO 2 Standard Dielectric Low-K Dielectric 500 500 3 µ m 1.5 µ m 0.75 µ m 400 400 3 µ m 0.75 µ m 1.5 µ m 0 C] 0 C] 300 300 ∆ T [ ∆ T [ 200 200 Metal 1 ∆ ∆ ∆ ∆ ∆ ∆ Metal 1 Standard 100 Low-k 100 Dielectric Dielectric 0 0 0 1 2 3 0 1 2 3 Power [W] Power [W] � As W decreases SH increases. � Low-k increases SH by 10-15% ISPD 2001 ISPD 2001 K. Banerjee, M. Pedram and A. H. Ajami
Scaling Trends and Implications Scaling Trends and Implications � Scaling Effects (ITRS ’99) � Chip Power and Area increases � Negligible Change in Power Density � Current Density in Metal Lines Increases � Number of Metal Levels Increases Chip Temperature Distribution ? � As Temperature Increases � Electromigration (EM) Time to Failure Decreases � Increased ρ ρ ρ ρ (T) Wire Delay Increases ISPD 2001 ISPD 2001 K. Banerjee, M. Pedram and A. H. Ajami
Scaling Effects (1) : Scaling Effects (1) : Thermal Conductivity of Dielectrics Thermal Conductivity of Dielectrics 1.2 1.2 Thermal Conductivity Thermal Conductivity SiO 2 1.0 1.0 HSQ 0.8 0.8 [W/m·K] [W/m·K] 0.6 0.6 Polyimide ( ITRS ’99 ) 0.4 0.4 Air 0.2 0.2 130 nm 180 nm 100 nm 100-130 nm 0.0 0.0 70 nm <50 nm 1.0 1.0 1.5 1.5 2.0 2.0 2.5 2.5 3.0 3.0 3.5 3.5 4.0 4.0 Dielectric Constant ( ε Dielectric Constant ( ε ε ) ε ) ε ε ε ε ISPD 2001 ISPD 2001 K. Banerjee, M. Pedram and A. H. Ajami
Full Chip Thermal Analysis Full Chip Thermal Analysis ● Three Dimensional Heat Conduction Cu IMD q ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ ● Steady State, Uniform Heat Interconnect Interconnect Generation (q’’’), Constant Properties (k) ILD ILD ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ q 2 2 ∇ ∇ ∇ ∇ + + + + = = = = ∇ ∇ ∇ ∇ T = = = = T 0 , 0 P/A k ( Interconnect ) ( Others ) ILD ILD z ● Worst Case Simulation Si Substrate Si Substrate – Uniform j rms for all Metal y x Lines ( ITRS ’99 ) T Die ISPD 2001 ISPD 2001 K. Banerjee, M. Pedram and A. H. Ajami
Scaling Effects (2) : Scaling Effects (2) : Maximum Chip Temperature Maximum Chip Temperature (IEDM 2000) ● Negligible 250 250 250 1.0 1.0 1.0 Power Density [W/mm 2 ] Power Density [W/mm 2 ] Change in Temperature [°C] Temperature [°C] Power Density 200 200 200 0.8 0.8 0.8 T max T max ( ITRS ’99 ) 150 150 150 0.6 0.6 0.6 ● T Die = 133±15°C T Die T Die 100 100 100 0.4 0.4 0.4 ● Increase in T max 50 50 50 0.2 0.2 0.2 Due to Joule Heating of 0 0 0 0.0 0.0 0.0 Interconnects 35 35 35 50 50 50 100 100 100 130 130 130 70 70 70 180 180 180 ( FEM Simulation ) Technology Node [nm] Technology Node [nm] ISPD 2001 ISPD 2001 K. Banerjee, M. Pedram and A. H. Ajami
Scaling Effects (3) : Scaling Effects (3) : Temperature Distribution Temperature Distribution (IEDM 2000) 220 220 209 °C 50 nm Temperature [°C] 200 200 Global Wires 35 nm Global Wires 180 180 70 nm 100 nm 160 160 130 nm 140 140 180 nm 126 °C 120 120 0 0 0 1 1 1 2 2 2 3 3 3 4 4 4 5 5 5 6 6 6 7 7 7 8 8 8 9 9 9 10 10 10 50 nm Node Distance from Substrate [ µ µ µ µ m] ISPD 2001 ISPD 2001 K. Banerjee, M. Pedram and A. H. Ajami
Scaling Effects (4) : Effects on Scaling Effects (4) : Effects on Reliability & Performance Reliability & Performance (IEDM 2000) 100 100 100 50 50 50 % Increase in RC Delay % Increase in RC Delay % Decrease in TTF % Decrease in TTF 80 80 80 40 40 40 60 60 60 30 30 30 40 40 40 20 20 20 20 20 20 10 10 10 0 0 0 0 0 0 35 35 35 50 50 50 70 70 70 100 100 100 130 130 130 180 180 180 35 35 35 50 50 50 70 70 70 100 100 130 130 130 180 180 180 100 Technology Node [nm] Technology Node [nm] Technology Node [nm] Technology Node [nm] � − ρ ρ ρ ρ TTF ( T ) ( T ) � � � � � � � � � � � � � � � = = = = − − − max × × × × = = = = max − − − − × × × × % D in TTF 1 100 % I in RC Delay 1 100 ρ ρ ρ ρ TTF ( T ) ( T ) � � � � � � � � � � � � � � � � Die Die � � � � � � � � � � � � � � � � ISPD 2001 ISPD 2001 K. Banerjee, M. Pedram and A. H. Ajami
Scaling Trends and Implications Scaling Trends and Implications (Summary) (Summary) � Scaling trends that cause increasing thermal effects: � increasing interconnect levels � increasing current density � low-k dielectrics � increasing thermal coupling ISPD 2001 ISPD 2001 K. Banerjee, M. Pedram and A. H. Ajami
Presentation Outline Presentation Outline � Introduction � Thermal Effects and Reliability � Interconnect Performance Optimization � High-Current Effects: ESD � Analysis of Non-uniform Chip Temperature � Temperature Dependent Performance � Circuit Optimization: Clock Skew � Summary ISPD 2001 ISPD 2001 K. Banerjee, M. Pedram and A. H. Ajami
Reliability Implications Reliability Implications Electromigration (EM) � Transport of mass in metal interconnects under an applied current density � EM lifetime reliability modeled using Black’s Q equation given by, − − − − n � � � � � � � � = = = = TTF A j exp � � � � � � � � k T B m � � � � � � � � TTF is the time-to-fail A is a constant that depends on line geometry and microstructure j is the DC or average current density Q is the activation energy for EM ( ~ 0.7 eV for AlCu) T m is the metal temperature ISPD 2001 ISPD 2001 K. Banerjee, M. Pedram and A. H. Ajami
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