TEG: A New Post-Layout TEG: A New Post-Layout Optimization Method - PDF document

TEG: A New Post-Layout TEG: A New Post-Layout Optimization Method Optimization Method Shuo Zhang Wayne Dai April 8, ISPD’02 Outline Outline � Design optimization in post-layout stage � TEG: A new post-layout optimization method � Topological layout and operations in TEG � Experimental results � Conclusion April 8, ISPD’02 2 1

Physical Design Flow Physical Design Flow IO Pad Placement Floorplanning Power/Ground Routing Placement Clock Tree Synthesis Post- -layout: layout: Post Global Routing after detail routing, after detail routing, precise wire geometry precise wire geometry information is available. information is available. Detail Routing April 8, ISPD’02 3 PD:Verification vs. Modification PD:Verification vs. Modification estimated estimated IO Pad Placement easy easy Floorplanning Verification Verification Modification Modification Power/Ground Routing Design Design Design Design Placement Clock Tree Synthesis Design Global Routing Optimization difficult difficult accurate accurate Detail Routing Extraction and Verification April 8, ISPD’02 4 2

Post-layout Optimization Post-layout Optimization � Whether the design can be verified and analyzed precisely? � What and where is the design problem? � What layout optimization or modification should be performed? � How modifications can be achieved with geometry constraints all over the layout? April 8, ISPD’02 5 TEG: A Post-layout Optimization Method TEG: A Post-layout Optimization Method Geometry Extraction & Detail Routing Layout Verification layout problems Post-layout Optimization Topological TEG TEG Layout April 8, ISPD’02 6 3

Layout: Geometry vs. Topological Layout: Geometry vs. Topological Topological Geometry � Each net has determined � Each net has wiring topology. geometry path. � Wiring topology: relationships Net path: a sequence of hard between wires and layout � wire segments. features. � No geometry wire, no wire � Any layout change is restrained constraints. by surrounding wire segments. April 8, ISPD’02 7 Topological Layout Optimization Flow Topological Layout Optimization Flow Geometry Extraction & Detail Routing Layout Verification layout geometry topology problems transform extraction Post-layout Topological Optimization Topological Layout DRC TEG TEG DRVS layout operations Layout DRV Solver Modification remove DRVS April 8, ISPD’02 8 4

Topological Layout Encoding Topological Layout Encoding 1 1 1 3 2 4 0 4 Geometry RBS Yu’s � Rubber Band Sketch: represents wires as rubber-bands. + Clear and straightforward layout change operation. – Data size grows dramatically as design size increases. � Yu’s encoding (1997): represents wire paths as the numbers of crossing wires on each triangulation edge. + Data size is significantly decreased. – Many computations are required. – Only support uniform design rule. April 8, ISPD’02 9 TEG: Triangulation Encoding Graph TEG: Triangulation Encoding Graph Geometry TEG TEG: Improved from Yu’s, representing wires as crossing points between wire path and edges in the layout triangulation. + Capability: Designed for the large scale applications A small design (3k nets/8.6k pins) RBS:TEG:Yu = 2.7:1.1:1.0 Large scale designs TEG/Yu = 105% ~ 114% + Practicability: Support multiple spacing/width, practical design rules + Efficiency: Good support for topological layout operations Design rule check, DRV solver, layout change, topology extraction April 8, ISPD’02 10 5

Topological Design Rule Check Topological Design Rule Check � DRC: Whether a topological layout represents a valid geometry layout without any design rule violations (ROUTABILITY). � Classic Routability Theorem (Maly 1990): A layout is routable if and only if all cuts are safe. O(n 2 ) cuts, n – number of features w 1 w 2 w 3 f a f b Sa1 S12 S23 S3b flow capacity A cut is safe: flow <= capacity, otherwise it is a DRV April 8, ISPD’02 11 TEG: Sealing Pair Routability Theorem TEG: Sealing Pair Routability Theorem s ( v 1 , sv 2 ), ( v 2 , sv 1 ) Sealing pair ( s, e ) v 1 v 2 e semi-open area op � SP: a vertex-edge pair of a triangle in the layout triangulation. � SP Status: unsealed -- a DRV is found in the determining process sealed -- each cut between s and any vertex inside op is safe if there is no DRV between inside op. � A layout is routable if all SPs are sealed in TEG. O(n) SPs � To determine the status of one SP, it is a recursive process with constant time in each recursive-call. � Experimental results show there are totally O(n) recursive-calls. April 8, ISPD’02 12 6

TEG: Design Rule Violation Solver TEG: Design Rule Violation Solver � A DRV: not enough layout resource in the local area, defined by surrounding features (terminals, vias…). � DRV Solver: Move resource to the Geometry violation area; move TEG DRV toward the resource area. � DRV solvers gives each layout change as much resource as possible from the global view of the layout. April 8, ISPD’02 13 TEG: Layout Modification TEG: Layout Modification � Core change operation in TEG: Vertex-moving � Key element in DRV solver � Via relocation, obstacle/cell moving, buffer insertion… � Vertex-moving algorithm � Triangulation reconstruction and encoding update � Running time: O(m·n) , n – number of wires, m – number of vertices influenced by moving. April 8, ISPD’02 14 7

Experimental Results Experimental Results 350 300 250 #Cells (K) #Nets (K) 200 #Pins (K) 150 TEG (MB) 100 50 0 D1 D2 D3 D4 D5 D6 Examples: Cells (4.9K ∼ 134K), Nets (5.0K ∼ 41.8K), Pins (26K ∼ 330K) April 8, ISPD’02 15 Running Time - Setup Running Time - Setup 1. Import the original routed design (LEF/DEF) into TEG. 2. Modification: 500 randomly selected via-moving 3. Topological DRC then DRV solver 4. Geometry Transform. PIII 550, 768MB memory, Linux platform April 8, ISPD’02 16 8

Running Time Running Time seconds 500 450 400 Import 350 Mod. 300 DRC 250 Solver 200 G-Trans 150 100 50 0 D1 D2 D3 D4 D5 D6 Mod: 5000 via-moving, DRC: ~30000 SPs, Solver: 10 DRVs April 8, ISPD’02 17 Layout D1 (~5%) in Cadence SE Layout D1 (~5%) in Cadence SE April 8, ISPD’02 18 9

Layout D1 (~5%) in TEG Layout D1 (~5%) in TEG April 8, ISPD’02 19 Wire Sizing by TEG Wire Sizing by TEG After wire sizing Original Layout Original Layout After wire sizing Fix crosstalk-delay, reduce IR-drop … April 8, ISPD’02 20 10

Wire Distribution by TEG Wire Distribution by TEG Original Layout Original Layout After wire distribution After wire distribution Reduce wire density difference: decrease CMP process variation, improve yield and manufacturability… April 8, ISPD’02 21 Conclusion Conclusion � In post-layout stage, the challenge is how to achieve preferred layout modifications: even the small change is not acceptable due to the limited local resource. � TEG: A new post-layout optimization method which processes the layout topologically, with an improved topological layout encoding mode and a set of layout operation procedures. � TEG provides an incremental layout modification environment for post-layout optimizations. � TEG is efficient and effective for industry IC designs. April 8, ISPD’02 22 11