Adding VHDL support to Icarus Verilog Maciej Sumiski, CERN FOSDEM, - PowerPoint PPT Presentation

Adding VHDL support to Icarus Verilog Maciej Sumiński, CERN FOSDEM, Brussels, 1.02.2015

Icarus Verilog ● FOSS hardware description language simulator ● Lead developer: Stephen Williams ● Written in C/C++ (& flex/bison/gperf) ● Great coverage of Verilog (IEEE 1364- 1999/2001/2005) ● Active work on SystemVerilog (IEEE 1800- 2005/2009/2012)

Goal ● GHDL = VHDL simulator ● Icarus = Verilog & SystemVerilog simulator ● ? = mixed-mode simulator

Icarus principles iverilog adder.vhd adder_test.v iverilog iverilog

Icarus principles iverilog adder.vhd adder_test.v iverilog ivlpp iverilog ivlpp

Icarus principles iverilog adder.vhd adder_test.v iverilog ivlpp iverilog ivlpp vhdlpp vhdlpp

Icarus principles iverilog adder.vhd adder_test.v iverilog ivlpp ivl iverilog ivlpp ivl vhdlpp vhdlpp

Icarus principles iverilog adder.vhd adder_test.v Targets : vvp vvp sizer sizer iverilog ivlpp ivl iverilog ivlpp ivl fpga fpga . . . vhdlpp vhdlpp vlog95 vlog95

Icarus principles iverilog adder.vhd adder_test.v Targets : Simulation : vvp a.out vvp vvp a.out vvp sizer sizer iverilog ivlpp ivl iverilog ivlpp ivl fpga fpga . . . vhdlpp vhdlpp vlog95 vlog95

Icarus principles iverilog adder.vhd adder_test.v Targets : Simulation : vvp a.out vvp vvp a.out vvp sizer sizer VPI VPI iverilog ivlpp ivl iverilog ivlpp ivl fpga fpga . . . vhdlpp vhdlpp vlog95 vlog95 Custom Custom modules modules

vhdlpp - example library ieee; module \mux2to1 (input wire use ieee.std_logic_1164.all; logic \i0 , input wire logic \i1 , entity mux2to1 is input wire logic \s , port( output logic \y ); i0, i1, s: in std_logic; always begin y: out std_logic); case (\s ) end mux2to1; 1'b0: \y <= \i0 ; architecture mux2to1_rtl of default: mux2to1 is \y <= \i1 ; begin endcase process (i0, i1, s) @(\i0 , \i1 , \s ) /* begin sensitivity list for process case (s) is */; when '0' => y <= i0; end when others => y <= i1; endmodule end case; end process; end mux2to1_rtl;

vhdlpp Adding new features: ● Parser rules ● Elaborate ● Emit

Status ● Procedures & functions ● Loops, including for .. generate ● Typedefs / subtypes ● Arrays, records ● Some of attributes (e.g. 'event, 'range) ● 80+ tests for VHDL & over 2000 for Verilog & SV

Alternative approach VHDL files GHDL VHDL files GHDL Simulation Simulation Object files? Object files? results results LLVM IR code? Verilog & LLVM IR code? Verilog & Icarus Icarus SystemVerilog SystemVerilog Verilog Verilog files files Common runtime Common runtime library library

Another method GHDL GHDL VHDL files VHDL files Simulation Simulation Main driver Main driver results results Verilog & Verilog & SystemVerilog SystemVerilog files files Icarus Icarus Verilog Verilog

More information In a Nutshell, Icarus Verilog... ...has had 7,561 commits made by 36 contributors representing 175,756 lines of code ...is mostly written in C++ ● Official website with an average number of source code comments ...has a well established, mature codebase maintained by a large development team http://iverilog.icarus.com/ with increasing Y-O-Y commits ...took an estimated 46 years of effort (COCOMO model) ● Wiki starting with its first commit in November, 1998 ending with its most recent commit 22 days ago http://iverilog.wikia.com/ [source: https://www.openhub.net/p/iverilog] ● Github repository: https://github.com/steveicarus/iverilog/ https://github.com/steveicarus/ivtest/