A Smart Port Card Tutorial --- Hardware John DeHart Washington University jdd@arl.wustl.edu http://www.arl.wustl.edu/~jdd Washington SPC Tutorial 1 July 7/8 2000 WASHINGTON UNIVERSITY IN ST LOUIS References: New Links from Kits References Page • Intel Embedded Module: – Data Sheet – Design Guide • 430HX Chipset – NorthBridge – SouthBridge • System FPGA • Memory • Mobile Pentium with MMX – Software Developer Manuals 1,2,3 – Datasheet • APIC • Cache Washington SPC Tutorial July 7/8 2000 2 WASHINGTON UNIVERSITY IN ST LOUIS page 1
Motivation • Active Networking • Network Probe • High performance router architectures – PC as router is VERY limited – (Gigabit/s + Processing) on each port – MSR: Multi-Service multiport Router Washington SPC Tutorial 3 July 7/8 2000 WASHINGTON UNIVERSITY IN ST LOUIS The Smart Port Card • Hardware: – SPC as a PC • How do they each boot? – SPC Hardware Components • What roles do they play? Washington SPC Tutorial July 7/8 2000 4 WASHINGTON UNIVERSITY IN ST LOUIS page 2
Typical Pentium PC CPU/Memory Bus Addr/Data Ctrl Ctrl North- Cache CPU DRAM Bridge Addr/Data/Ctrl PCI Bus NMI INIT Intr PCI SouthBridge (PIIX3) Devices (PIC, PIT, …) ISA Bus ISA Super-IO BIOS BIOS Devices Kbd/Mse Parallel Floppy Uarts RTC ... Washington SPC Tutorial 5 July 7/8 2000 WASHINGTON UNIVERSITY IN ST LOUIS How NetBSD Boots on a PC Components: – Pentium – Boot ROM (replaced by BIOS in modern systems?) – BIOS – Bootloader – Kernel Washington SPC Tutorial July 7/8 2000 6 WASHINGTON UNIVERSITY IN ST LOUIS page 3
Sketch of How a PC Boots … at least what I understand… • Pentium after Reset: – fetches its first instruction from location 0xFFFFFFF0 • Boot Code must be located at 0xFFFFFFF0 • Boot Code jumps to BIOS located in ROM – Boot Code may actually be part of the BIOS... • BIOS copies itself into memory (Shadow) • BIOS remaps memory – future accesses to BIOS addresses go to memory instead of ROM. • BIOS performs system configuration (some proprietary) – Motherboard Details – Pentium Details – NB/SB Chipset Details – Device configuration: IRQs, Memory maps, ... Washington SPC Tutorial 7 July 7/8 2000 WASHINGTON UNIVERSITY IN ST LOUIS How a PC Boots (continued…) • BIOS loads bootloader into memory (from disk…) • BIOS jumps to bootloader • Bootloader performs some more configuration: – Pentium control registers – Cache configuration – Memory/Page model • Bootloader determines what to run next. • Bootloader may have to do some device configuration. – e.g. to get OS from a disk. • Bootloader loads OS kernel into memory • Bootloader jumps to start of OS kernel Washington SPC Tutorial July 7/8 2000 8 WASHINGTON UNIVERSITY IN ST LOUIS page 4
How a PC Boots (continued…) • Kernel does some OS-specific configuration: – for NetBSD look in: sys/arch/i386/i386/locore.s – Determines what CPU it has (“cpuid” instruction) – Paging – Virtual Memory Washington SPC Tutorial 9 July 7/8 2000 WASHINGTON UNIVERSITY IN ST LOUIS Typical Pentium PC (Again…) CPU/Memory Bus Addr/Data Ctrl Ctrl North- Cache CPU DRAM Bridge Addr/Data/Ctrl PCI Bus NMI INIT Intr PCI SouthBridge (PIIX3) Devices (PIC, PIT, …) ISA Bus ISA Super-IO BIOS BIOS Devices Kbd/Mse Parallel Floppy Uarts RTC ... Washington SPC Tutorial July 7/8 2000 10 WASHINGTON UNIVERSITY IN ST LOUIS page 5
What SPC Needs CPU/Memory Bus Addr/Data Ctrl Ctrl North- Cache CPU DRAM Bridge Addr/Data/Ctrl PCI Bus NMI Intr INIT APIC SouthBridge (PIC, PIT, …) BIOS BIOS Uarts RTC Washington SPC Tutorial 11 July 7/8 2000 WASHINGTON UNIVERSITY IN ST LOUIS SPC Architecture Addr/Data Ctrl Ctrl North- Cache CPU DRAM Bridge Addr/Data/Ctrl Intel Embedded Module PCI Bus INIT NMI Intr APIC RTC’ PIC PIT UART1 UART1 Interface BIOS ROM Link Interface UART2 UART2 Interface System FPGA Switch Interface Washington SPC Tutorial July 7/8 2000 12 WASHINGTON UNIVERSITY IN ST LOUIS page 6
SPC Photo Tour Switch Interface DRAM Link Interface CPU Module APIC PCI Bus System FPGA Serial Ports Washington SPC Tutorial 13 July 7/8 2000 WASHINGTON UNIVERSITY IN ST LOUIS SPC Components • APIC • PCI Bus Master • Pentium Embedded Module – 166 MHz MMX Pentium Processor • L1 Cache: 16KB Data, 16KB Code – L2 cache: 512 KB – NorthBridge - 33 MHz, 32 bit PCI Bus • PCI Bus Master • System FPGA • PCI Bus Slave – Xilinx XC4020XL A -1 FPGA – 20K Equivalent Gates – ~ 75% used Washington SPC Tutorial July 7/8 2000 14 WASHINGTON UNIVERSITY IN ST LOUIS page 7
SPC Components (continued) • Memory – EDO DRAM – 64MB (Max for current design) – SO DIMM • Switch Interface - 1 Gb Utopia • Link Interface - 1 Gb Utopia • UART – Two Serial Ports • NetBSD system console • TTY port Washington SPC Tutorial 15 July 7/8 2000 WASHINGTON UNIVERSITY IN ST LOUIS System FPGA • Coded in VHDL • PCI slave device • Replaces some of the PIIX3 (south bridge) • Replaces some of the BIOS • Replaces some of the Super IO Chip • Provides reset capability Washington SPC Tutorial July 7/8 2000 16 WASHINGTON UNIVERSITY IN ST LOUIS page 8
System FPGA: PIIX3 Functionality • Programmable Interrupt Controller (PIC) – Four Interrupts supported and statically assigned: • PIT (IRQ 0) • APIC (IRQ 5) • COM1 (IRQ 4) • COM2 (IRQ 3) – Static fully-nested interrupt priority structure. – Specific End of Interrupt is the only EOI mode supported • Programmable Interval Timer (PIT) – generates a clock interrupt for NetBSD every ~10ms • Reset - covered in a later slide Washington SPC Tutorial 17 July 7/8 2000 WASHINGTON UNIVERSITY IN ST LOUIS System FPGA: BIOS Functionality • Interrupt functionality replaced by static values • Simple 16 word by 32-bit “ROM” – implements loop waiting for location 0xFFE00 to change value – then jumps to boot loader code • Does NOT perform configuration of Northbridge – This will be done by the boot loader • Does NOT perform PCI configuration of APIC – This will be done by the APIC Driver Washington SPC Tutorial July 7/8 2000 18 WASHINGTON UNIVERSITY IN ST LOUIS page 9
System FPGA: Super IO Chip Functionality • UART Interface – Two Serial lines supported – Fixed IRQs • Real Time Clock – only the register accesses of the RTC are supported – no interrupts supported – i.e. supported only so NetBSD didn’t need to change – i.e. no alarms will be generated Washington SPC Tutorial 19 July 7/8 2000 WASHINGTON UNIVERSITY IN ST LOUIS System FPGA: Reset • SPC needs a reset before every download: – switch reset: • causes SPC to be reset • causes all connections in switch to be lost – System FPGA reset • causes SPC to be reset • has no effect on the switch • Normal SouthBridge reset: – I/O Register : 0xCF9 – Hard Reset: assert CPURST, PCIRST#, and RSTDRV • write 0xCF9 0x02 (00000010b) • write 0xCF9 0x06 (00000110b) bits – Soft Reset: assert INIT • write 0xCF9 0x00 (00000000b) • write 0xCF9 0x04 (00000100b) Washington SPC Tutorial July 7/8 2000 20 WASHINGTON UNIVERSITY IN ST LOUIS page 10
System FPGA: Reset • SPC Reset: – a sequence of two writes to memory addresses – APIC Control cells can write to • memory addresses • configuration registers • NOT I/O Registers! Argh... – To mimic the reset structure of the SB we use: • 0xFFFFFFF0 • 0xFFFFFFF4 – Hard Reset (all we really care about) • write 0xFFFFFFF0 0x02 (00000010b) bits • write 0xFFFFFFF4 0x06 (00000110b) Washington SPC Tutorial 21 July 7/8 2000 WASHINGTON UNIVERSITY IN ST LOUIS Caveats • Intel Embedded Module problem – Memory corruption caused by noise on M/A bus – Hopefully it will be fixed before we ship – We work around it with 25 MHz PCI and no HLT • This reduces the probability of noise on the bus • PCI Bus – 33 MHz vs. 25 MHz • NetBSD Kernel HLT instruction – if absolutely nothing to do, NetBSD does a “HLT” – this reduces power consumption – also causes large power/current swings – We have removed the HLT instruction for the SPC • Serial Cables – RS232 is not necessarily hot-swappable • sometimes you can get away with it but not always Washington SPC Tutorial July 7/8 2000 22 WASHINGTON UNIVERSITY IN ST LOUIS page 11
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